Sanyo Electric Co., Ltd.

Semiconductor Components Industries, LLC

National Institute of Advanced Industrial Science and Technology

Hideaki Fujiwara

Kouichi Yamada

Yasuhiro Takeda

Akira Toriumi

Toru Dan

Haruki Yoneda

Shoji Sudo

Hideharu Nagasawa

Sadao Kondo

Takashi Hiroshima

Shinya Naito

A semiconductor device (npn bipolar transistor) includes an n-type collector layer, a base layer constituted by a pdiffusion layer, a SiGe layer and a p-type silicon film, an n-type emitter layer and a charge transport prevention film formed between the n-type collector layer and the n-type emitter layer and having an effect as a potential barrier with respect to either electrons or holes.

Semiconductor device

A capacitor includes a positive electrode base material, a dielectric layer, a positive electrode body, a dielectric layer, a negative electrode body, and a negative electrode base material. The positive electrode body is formed on the positive electrode base material and in part is in contact with the positive electrode base material. The positive electrode body is formed by association of a large number of metal particles, and the associated metal particles form a reticular network. The positive electrode base material and the positive electrode body (core part) are formed of a NiTi alloy containing Ni having a large work function. The dielectric layers (high-permittivity insulating film) are formed of titanium oxide. It is preferable that at least one Ni atomic layer is formed at an interface between the high-permittivity insulating film and the core part. Although the Ni atomic layer is preferably formed over the entire interface, the Ni atomic layer may be partially formed at the interface.

Electrode for capacitor and capacitor

A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter (E), the base (B) receiving an output of the inverter.

A semiconductor device capable of reducing deterioration of electron mobility while suppressing depletion of gate electrodes is provided. This semiconductor device includes a metal-containing layer so formed that at least either a first gate electrode or a second gate electrode partially covers a corresponding first or second gate insulating film and a semiconductor layer formed on the metal-containing layer to come into contact with a portion of the corresponding first or second gate insulating film not covered with the metal-containing layer. The first and second gate electrodes contain metals different from each other.

Semiconductor device comprising gate electrode

A semiconductor device capable of reducing a threshold voltage is obtained. The semiconductor device includes a pair of source/drain regions formed on the main surface of a semiconductor region to hold a channel region therebetween, and a gate electrode formed on the channel region through a gate insulating film and including a metal-containing layer arranged in the vicinity of an interface between the gate insulating film and the gate electrode, wherein the metal-containing layer is so formed in the form of dots as to partially cover the surface of the gate insulating film, and the average distance between dots forming the metal-containing layer is set to not more than a diameter of the dot of the metal-containing layer.

A semiconductor device capable of inhibiting a threshold voltage from increase also when employing a gate electrode consisting of a metal is provided. This semiconductor device comprises a pair of source/drain regions lifted up in an elevated structure, a gate insulator film, formed on a channel region, consisting of a high dielectric constant insulator film having a dielectric constant larger than 3.9 and a gate electrode including a first metal layer coming into contact with the gate insulator film and having a work function controlled to have a Fermi level around the energy level of a band gap end of silicon constituting the source/drain regions.

Semiconductor device including field-effect transistor

A semiconductor memory capable of attaining a low voltage, a high-speed operation, low power consumption and a high degree of integration is obtained. This semiconductor memory comprises a floating gate electrode, a first source/drain region having a diode structure employed for controlling the potential of the floating gate electrode and a second source/drain region formed to hold a channel region between the same and the first source/drain region. Thus, when a channel of a transistor is turned on in reading, a large amount of current flows from the first source/drain region having a diode structure to a substrate, whereby high-speed reading can be implemented. Further, a negative voltage is readily applied to the first source/drain region having a diode structure, whereby a low voltage and low power consumption are attained and the scale of a step-up circuit is reduced, and hence a high degree of integration can be attained.

Semiconductor memory and semiconductor device

A semiconductor memory capable of increasing the coupling ratio between a diffusion layer and a floating gate by reducing the coupling ratio between the floating gate and a control gate thereby easily performing high-speed writing with a low diffusion layer voltage is provided. This semiconductor memory comprises the floating gate, a first diffusion layer capacitively coupled with the floating gate for controlling the potential of the floating gate and the control gate arranged oppositely to the floating gate. In an erase operation, the control gate feeds a tunnel current to the floating gate in a direction substantially parallel to the main surface of a semiconductor substrate. Thus, the tunnel current can be fed by extracting carriers from the floating gate also when the control gate has no region overlapping with the upper portion of the floating gate.

Nonvolatile semiconductor memory

There is disclosed a method of forming an isolation film in a semiconductor device, the method including the steps of: forming a silicon oxide film and a silicon nitride film in that order on a silicon substrate, using a resist pattern as a mask, etching the silicon nitride film and silicon oxide film, and forming trenches in the substrate. In the substrate, the respective trenches form a region in which isolation films are to be formed, and the region between the trenches forms an active region. In this case, each dimension is set so that a ratio W/t of width W to thickness t of the patterned silicon nitride film is 3.8 or more. Subsequently, by removing the resist pattern, subsequently using the silicon nitride film as the mask, and performing thermal oxidation at a temperature of 1050&deg; C. to 1150&deg; C. in an oxygen atmosphere, an isolation film is formed in the trench.

Method of forming isolation film in semiconductor device

A coupling coefficient measuring method for a semiconductor memory capable of directly measuring a coupling coefficient in an actual cell without employing a specific test structure including a non-floating gate electrode or the like is obtained. In this coupling coefficient measuring method for a semiconductor memory, first and second subthreshold currents are measured by changing a drain voltage and increasing a source voltage and thereafter a first source voltage corresponding to a first value of the first: subthreshold current and a second source voltage corresponding to a second value of the second subthreshold current equal to the first value are read while the ratio of the difference between the first drain voltage and the second drain voltage to the difference between the first source voltage and the second source voltage is calculated. Thus, the coupling coefficient between the first gate electrode and a source region can be obtained in an actual cell without providing a specific test structure including a non-floating gate electrode or the like, dissimilarly to the prior art.

Coupling coefficient measuring method and coupling coefficient measuring apparatus for semiconductor memory

A memory cell in a simple structure having a long life, less variations in the structure and writing characteristic, and a higher operation speed, free from the problem of over-erasure, and permitting down-sizing is disclosed. Floating gate electrodes are arranged on a channel region with a gate insulating film therebetween. A control gate is formed on the floating gate electrodes with a tunnel insulating film therebetween. A central part of the control gate electrode is provided on the channel region to form a select gate. Source/drain regions having the select gate therebetween and the select gate form a select transistor. The coupling capacitance between each of the floating gate electrodes and the control gate electrode is set much larger than the coupling capacitance between each of the floating gate electrodes and the substrate.

Transistor, transistor array and non-volatile semiconductor memory

A semiconductor memory capable of attaining a long life, a low voltage, a high-speed operation, low power consumption and high integration is provided. The semiconductor memory comprises a control gate electrode, a floating gate electrode, a semiconductor region, a first insulator film formed on one surface of the semiconductor region and a second insulator film formed on another surface of the semiconductor region. A prescribed voltage is applied to the control gate electrode or a drain region thereby injecting carriers from the control gate electrode or the drain region into the floating gate electrode through the first insulator film, the semiconductor region and the second insulator film.

Semiconductor memory and method of operating semiconductor memory

A non-volatile semiconductor memory device accurately stores multivalued data with reduced damage to an insulating layer. The non-volatile semiconductor memory device includes a floating gate electrode configured to be divided into at least two portions. The first portion is employed for accumulating carriers migrating from at least one control gate electrode through a gate insulating layer to the floating gate electrode.

Non-volatile semiconductor memory devices

A semiconductor device includes a semiconductor substrate, source and drain regions defined in the semiconductor substrate with a channel region therebetween, a first insulating layer located over the semiconductor substrate including over the channel region, a floating gate locating over the first insulating layer, a second insulating layer located over the floating gate, a first control gate located over the second insulating layer, a third insulating layer located over the first control gate, a second control gate located over the third insulating layer. The first and second control gates allow the injection of hot carriers onto the floating gate from the first control gate when predetermined first and second voltages are applied to the first and second control gates, respectively.

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Hashima, Japan

Hideaki Fujiwara