Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Renesas Electronics Corporation

Nec Electronics Corporation

Hideaki Arima

Natsuo Ajika

Atsushi Hachisuka

Masahiro Shimizu

Yoshinori Tanaka

Tomonori Okudaira

Makoto Ohi

Yoshinori Okumura

Kaoru Motonami

Yasushi Matsui

Mitsuya Kinoshita

Tatsuo Okamoto

Yuichi Nakashima

Kazuyuki Sugahara

Kiyoteru Kobayashi

Ikuo Ogoh

Hideki Genjo

Kohjiroh Yuzuriha

Tadashi Nishimura

Shinichi Satoh

Takaaki Fukumoto

Hirofumi Shinohara

Takahisa Eimori

Yoshihiro Hirata

Kiyoto Watabe

Masahiro Yoneda

Susumu Takano

Masahiko Takeuchi

Kenjyu Shimogawa

Kenichi Kuboyama

Toshihiko Funaki

Shuuichi Senou

A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.

Semiconductor apparatus configured to reduce data processing performance

A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface formed on a major surface of a semiconductor substrate to extend from a memory cell region to a peripheral circuit region thereof. A capacitor lower electrode is formed in the memory cell region to upwardly extend beyond the upper surface of the insulating film on the major surface of the semiconductor substrate. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. The upper surface of the insulating film is located between the top and bottom surfaces of the capacitor lower electrode part.

Semiconductor device comprising capacitor and method of fabricating the same

A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. A semiconductor device organized as just described, permits implementation having a high density of integration while ensuring the capacitor exhibits high reliability and a constant capacitance.

A semiconductor device according to a first aspect of the present invention includes: a first circuit that outputs a first output value having a majority of output values received from N (N is three or more odd numbers) pieces of data hold circuits receiving a same input value; and a second circuit that outputs a second output value which is less than the majority of output values received from the N pieces of the data hold circuits.

Semiconductor device, and failure detection system and failure detection method of data hold circuit

In a semiconductor or memory device, a first ODT (On Die Termination) circuit is provided between a termination voltage port and a command input port. A first ODT controlling circuit is connected between the termination voltage port and the first ODT circuit, and detects a level of a voltage applied to the termination voltage port and controls the first ODT circuit to connect the termination voltage port and the command input port based on the detection result.

Semiconductor memory device

Semiconductor device comprising a highly-reliable, constant capacitance capacitor

A high density semiconductor device is formed with a constant capacitor capacitance. The semiconductor device includes a memory cell region and a peripheral circuit region. An insulating film, having an upper surface, is formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode is formed in the memory cell region to upwardly extend beyond the upper surface of the insulating film on the major surface of the semiconductor substrate. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. The upper surface of the insulating film is located between the top surface and the bottom surface of the capacitor lower electrode part.

A semiconductor device, including a memory cell region and a peripheral circuit region, comprises an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. A semiconductor device organized, as just described, permits implementation having a high density of integration while ensuring the capacitor exhibits high reliability and a constant capacitance.

A gate insulating film in a memory cell portion is thicker than a gate insulating film in a peripheral circuitry. Source/drain of an MOS transistor in the memory cell portion have double-diffusion-layer structures, respectively, and source/drain of an MOS transistor in the peripheral circuitry have triple-diffusion-layer structures, respectively.

Integrated circuit having a memory cell transistor with a gate oxide layer which is thicker than the gate oxide layer of a peripheral circuit transistor

Obtained are a semiconductor device which can be implemented with high density of integration while ensuring a constant capacitor capacitance in high reliability and a method of fabricating the same. The semiconductor device, including a memory cell region and a peripheral circuit region, comprises an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode is formed in the memory cell region to upwardly extend beyond the upper surface of the insulating film on the major surface of the semiconductor substrate. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. The upper surface of the insulating film is located between the top surface and the bottom surface of the capacitor lower electrode part.

Integrated circuit having a memory cell transistor with a gate oxide

Growing community of inventors

Hyogo, Japan

Hideaki Arima