Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Hideaki Aochi

Yoshiaki Fukuzumi

Masaru Kito

Ryota Katsumata

Hiroyasu Tanaka

Masaru Kidoh

Megumi Ishiduki

Yosuke Komori

Tomoko Fujiwara

Ryouhei Kirisawa

Yasuyuki Matsuoka

Junya Matsunami

Yoshimasa Mikajiri

Shigeto Oota

Mitsuru Sato

Akihiro Nitayama

Tomoya Sanuki

Shiho Nakamura

Tsuyoshi Kondo

Jun Fujiki

Shinya Arai

Takuya Shimada

Masaki Tsuji

Susumu Hashimoto

Yoshihiro Ueda

Yasuaki Ootera

Yasuhito Yoshimizu

Shinji Miyano

Michael Arnaud Quinsat

Masaki Kado

Nobuyuki Umetsu

Yuichi Ito

Takeshi Imamura

Kaori Kawasaki

Yoshihisa Iwata

Takashi Maeda

Hirofumi Morise

Tsukasa Tada

Masaru Kido

Koji Asakawa

Satoshi Mikoshiba

Takeshi Kamigaichi

Reika Ichihara

Hideyuki Nishizawa

Masaki Kondo

Shigeki Hattori

Tomoo Hishida

Hiroyuki Fuke

Masaya Terai

Kiyotaro Itagaki

Mie Matsuo

Koichiro Shindo

Takashi Ohsawa

Takeshi Hamamoto

Kenichiro Yoshii

Ryo Fukuda

Nobutoshi Aoki

Keisuke Nakatsuka

Kazushige Kawasaki

Tomoaki Shino

Takayuki Okamura

Go Shikata

Hitoshi Ito

Kotaro Fujii

Tomoya Kawai

Sanae Ito

Hitomi Yasutake

Fumitaka Arai

Riichiro Shirota

Yoshio Ozawa

Ichiro Mizushima

Masumi Saitoh

Naomi Shida

Keiji Ikeda

Kiyotaka Miyano

Shinji Mori

Kenji Todori

Eiji Yoshida

Mitsuhiro Omura

Reiko Yoshimura

Hitoshi Iwai

Toshiharu Tanaka

Hiroki Tokuhira

Toshiyuki Enda

Shigehiko Mori

Hiroyoshi Tanimoto

Ko Yamada

Takamitsu Ishihara

Takashi Ishida

Yusuke Higashi

Takuji Kuniya

Hideki Inokuma

Naoki Kusunoki

Hideto Horii

Yoichi Takegawa

Kunihiro Yamada

According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

Semiconductor memory device having a circuit chip bonded to a memory array chip and including a solid-state drive controller and a control circuit

A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

Nonvolatile semiconductor memory device and manufacturing method thereof

A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Nonvolatile semiconductor memory device and method for manufacturing same

Semiconductor memory device having a contact plug electrically connected to an interconnection through a narrower via

According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.

Nonvolatile semiconductor memory device and method for driving same

A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

Semiconductor memory device and method for manufacturing the same

A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

Non-volatile semiconductor storage device and method of manufacturing the same

Method for reading data of a first memory cell transistor of a nonvolatile semiconductor memory device

Method for writing data of a first memory cell transistor of a nonvolatile semiconductor memory device

Semiconductor memory device including integrated control circuit and solid-state drive controller

Semiconductor device having a pad proximate to a step structure section of an array chip

A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.

Data latch circuit and semiconductor memory device

Growing community of inventors

Kawasaki, Japan

Hideaki Aochi