Samsung Electronics Co., Ltd.

Hi-Choon Lee

Byoung-Ju Kim

Wol-Jin Lee

Kwang-Hyun Kim

Kyung-Ho Kim

Chul-Woo Park

Won-Il Bae

Venkataramana Gangasani

Jae-Hyeong Lee

Won-Chang Jung

Sung-Min Yim

Vivek Venkata Kalluru

Seung-Cheol Oh

Sung-whan Seo

Joo-Sun Choi

Duk-ha Park

Sung-Bum Cho

A clock signal generation device includes a variable voltage providing circuit, a fixed voltage providing circuit and a clock signal generating circuit. The variable voltage providing circuit provides a variable reference voltage based on a selection signal, a reference voltage and a temperature coefficient. The variable reference voltage is varied according to temperature. The fixed voltage providing circuit provides a fixed reference voltage that is determined according to the selection signal. The fixed reference voltage is a constant voltage. The clock signal generating circuit provides a clock signal based on the fixed reference voltage and the variable reference voltage. The performance of the clock signal generation device may be increased by providing the clock signal based on the variable reference voltage that is varied according to the temperature and based on the fixed reference voltage.

Clock signal generation device and memory device including the same

In an embodiment, a semiconductor memory device includes a clock latency that can be controlled responsive to whether or not an output order of burst data is reordered. The semiconductor memory device may comprise a control unit and a latency control unit. The control unit may generate a latency control signal having a logic level that varies depending on whether or not an output order of burst data is reordered. The latency control unit may control a latency value in response to the latency control signal. The semiconductor memory device and the method of controlling the latency value responsive to a reordering of the burst data allow for an optimally fast memory access time.

Semiconductor memory device and method for controlling clock latency according to reordering of burst data

The present invention provides a semiconductor memory device comprising a memory cell array including a plurality of memory regions, an address decoding portion for decoding an address applied from an external portion for simultaneously selecting all of the plurality of memory regions during a test read operation, a data IO control portion for receiving test pattern data and writing the test pattern data to each of the plurality of memory regions during a test write operation, and reading the test pattern data from one of the plurality of memory regions and outputting the test pattern data during the test read operation, a data IO portion for receiving the test pattern data from the external portion and applying the test pattern data to the data IO control portion during the test write operation, and receiving the test pattern data output from the data IO control portion and conditionally outputting the test pattern data as test status data to the external portion in response to an output control signal during the test read operation, and a test control signal generating portion for comparing the test pattern data read from the plurality of memory regions to generate the output control signal for conditionally outputting the test pattern data as the test status data during the test read operation.

Semiconductor memory device

An integrated circuit device includes a test circuit and at least one flag generator circuit. The test circuit is configured to generate first and second sets of test results in parallel in response to a memory test operation. The first and second sets of test results respectively correspond to first and second memory banks. The test circuit is further configured to merge respective ones of the first set of test results with respective ones of the second set of test results to provide a set of merged test results to respective ones of a set of output terminals of the integrated circuit device. The at least one flag generator circuit is configured to generate a first flag signal that indicates a presence of at least one memory test error in the first set of test results, and a second flag signal that indicates a presence of at least one memory test error in the second set of test results. Based on the set of merged test results and the first and second flag signals, the test circuit may determine which of the memory blocks of the first and second memory banks includes a defective memory cell therein. Related methods are also discussed.

Parallel bit test circuits for testing semiconductor memory devices and related methods

A semiconductor memory device includes first and second global data line pairs connected to a local data line pair, allowing a reduced pre-charge voltage that lowers current consumption and increases operating speed. Also included are a sense amplifier for amplifying data of the second global data line pair and outputting the amplified data to a data line, and a write driver for outputting data of the data line to the first global data line pair during a write operation. Switching circuits are connected between the first and second global data line pairs, and the local data line and the first global data line pairs. The memory device further includes a first global data line pre-charge circuit for pre-charging the first global data line pair to a first voltage level, and a second global data line pre-charge circuit for pre-charging the second global data line pair to a second voltage level.

Semiconductor memory device and data read and write method thereof

A semiconductor memory integrated circuit includes a plurality of pads; a peripheral circuit having a plurality of control circuits which are arranged at locations adjacent to the plurality of the pads and receive a plurality of input signals to generate a plurality of output signals in response to a plurality of control signals, respectively; and a plurality of fuse circuits for generating the plurality of the control signals, said fuse circuits being arranged between the plurality of the pads and the peripheral circuit. Since the integrated circuit has the fuse circuits at a location adjacent to the pads, the characteristics of the IC can be changed even after the package test when a small region is opened.

Semiconductor memory integrated circuit and layout method of the same

The power noise removing circuit includes a decoupling capacitor group, a repair circuit unit, a monitoring pad, and a testing unit. The decoupling capacitor group includes a plurality of decoupling capacitors that store noise flowing into an internal power line. The decoupling capacitors are DRAM cell type capacitors. The repair circuit unit controls a connection of each of the decoupling capacitors in the decoupling capacitor group to an external input power line. The monitoring pad measures the amount of current leaking from the decoupling capacitor group. The testing unit controls a connection of the decoupling capacitor group to the monitoring pad. If the decoupling capacitor group is tested as being defective, the defective decoupling capacitor group is made inoperative by disconnection from the external input power line.

Semiconductor memory device having a circuit for removing noise from a power line of the memory device using a plurality of decoupling capactors

The semiconductor memory device includes an address change circuit, which is programmable to change a column address, and a column selection circuit, which generates first and second column selection signals addressing columns in first and second portions of a memory array based on the received column address from the address change circuit. When at least one column addressed by the column address in both of the first and second portions of the memory array includes a defective cell, the address change circuit can be programmed to change the address so that defective cells are not addressed.

Semiconductor memory devices with data line redundancy schemes and method therefore

A frequency divider divides the external clock signal by two and generates a first clock signal for an even-numbered data patch and a second clock signal for an odd-numbered data, wherein the first clock signal is opposite in phase to the second clock signal. A column selection line enable control circuit generates even-numbered column selection line enable signals in response to the first clock signal and generates odd-numbered column selection line enable signals in response to the second clock signal. A switching circuit connects a pair of bit lines to a pair of even-numbered input/output (I/O) lines in response to the even-numbered column selection line enable signals and connects the pair of bit lines to a pair of odd-numbered I/O lines in response to the odd-numbered column selection line enable signals. An I/O line sense amplification circuit senses and amplifies even-numbered read data from the pair of even-numbered I/O lines and outputs the amplified even-numbered read data to a pair of data lines in response to the first clock signal, and senses and amplifies odd-numbered read data from the pair of odd-numbered I/O lines and outputs the odd-numbered read data to the pair of data lines in response to the second clock signal.

Semiconductor memory device having high-speed input/output architecture

A semiconductor memory device with an improved redundancy scheme is provided. The semiconductor memory device includes at least one memory block having a plurality of memory banks that are arranged in a column direction. Each memory bank includes a plurality of normal memory cells, which are arranged according to a row and column structure, and at least one redundancy memory cell to replace defective memory cells. At least one memory bank, adjacent to an edge of photo shot or an edge of chip, among the plurality of memory banks includes more redundancy lines than the other memory banks. In the semiconductor memory device, when memory banks have different numbers of defective memory cells to be repaired, the number of redundancy memory cells of each memory bank is differently set, thus increasing the yield.

Semiconductor memory device having improved redundancy scheme

A semiconductor memory device that efficiently replaces defective word lines by redundancy word lines. The semiconductor memory device includes a plurality of banks, each bank having a plurality of normal word lines and a plurality of redundancy word lines. A defective word line can be replaced by the redundancy word lines when defects occur in the normal word lines. When word line defects occur, redundancy word lines banks adjacent to the bank having the defective work lines may be used.

Semiconductor memory device having improved replacement efficiency of defective word lines by redundancy word lines

A semiconductor memory device includes a plurality of sub-wordlines, a plurality of sub-wordlines corresponding a redundancy main wordline, a plurality of redundancy memory cells each being coupled to each of the redundancy sub-wordlines, and a redundancy control circuit for disabling the main wordline selector when among the sub-wordlines, a sub-wordline to which a defective memory cell is coupled is addressed, and for controlling the sub-wordline to be replaced by the redundancy main wordline. The number of the redundancy sub-wordlines coupled to the redundancy main wordline is smaller than the number of the sub-wordlines coupled to the main wordline. Therefore, when among the sub-wordlines coupled to the main wordline, a sub-wordline to which a normal main memory cell is coupled is addressed, the main wordline selector is enabled to improve a redundancy flexibility and reduce a circuit area.

A semiconductor memory device, which is capable of adjusting the number of banks from 2N to N and thus increasing product production and repair efficiency, and a method thereof are provided. The semiconductor memory device includes a switching circuit, a control circuit, and a redundant circuit. The switching circuit selectively transmits a first address or a second address in response to a control signal. The control circuit selectively activates 2 banks in response to N&minus; (where N is a natural number) bank selection addresses and the first address or selectively activates 2 banks in response to the N&minus;1 bank selection addresses. The redundant circuit controls repair of the defective normal memory cells. Each of the 2 banks comprises one memory block. Each of the 2 banks comprises 2 memory blocks, each of which is selectively activated in response to the second address. It is preferable that the defective normal memory cells are repaired in an activated bank in response to an output signal of the redundant circuit.

Semiconductor memory device capable of adjusting the number of banks and method for adjusting the number of banks

Internal signals for integrated circuits are generated by a reset circuit that is responsive to an input signal to generate a reset signal pulse a predetermined time after the input signal is activated, and a dynamic inversion circuit that inverts the input signal in the absence of the reset signal pulse and that assumes an inactive state in response to the reset signal pulse, to thereby produce an output pulse that is activated by the input signal and that is deactivated by the reset circuit as a function of the predetermined time. Methods of operating integrated circuits generate a reset signal pulse a predetermined time after an input signal is activated. The input signal is inverted until the reset pulse is generated, to thereby produce an output pulse that is activated by the input signal and that is deactivated by the reset circuit as a function of the predetermined time. Accordingly, circuits and methods for generating internal clock signals for integrated circuits by dynamic inversion and resetting can rapidly generate internal clock signals from external clock signals and can have reduced susceptibility to noise.

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Gyeonggi-do, South Korea

Hi-Choon Lee