Samsung Electronics Co., Ltd.

Heung Kyu Kwon

Sa Yoon Kang

Dong Hyeon Jang

Nam Seog Kim

Tae Je Cho

Hyeon J Jeong

Hee Seok Lee

Kyoung Mook Lim

Young Hoon Ro

Kyung Lae Jang

Hae Gu Lee

Dong Y Oh

Byeong Yeon Cho

A system module includes a printed circuit board (PCB), a first semiconductor chip embedded in the PCB, a semiconductor package connected to the PCB through a plurality of stack balls, and a second semiconductor chip disposed on a surface of the PCB in a space between the PCB and the semiconductor package.

System module and mobile computing device including the same

A system on package includes a first package and a second package stacked on the first package and electrically connected to one another through metal contacts. The first package includes a first printed circuit board (PCB), a system on chip which is connected to the first PCB through bumps, and a first memory device which is connected to the system on chip through micro bumps connected to vias in the system on chip. The second package includes a second PCB, a second memory device connected to the second PCB, a third memory device connected to the second PCB, and a memory controller which is connected to the second PCB and controls the third memory device.

System on package (SoP) having through silicon via (TSV) interposer with memory controller connected to multiple printed circuit boards (PCB)

A system on package SoP module includes a printed circuit board (PCB) having a first side and an opposing second side, a first IC attached to the first side, a second IC attached to the second side. The PCB also provides electrical paths for connecting the first IC and the second IC. Conductors by which the second IC is attached to the PCB also allow for electrical testing of the first IC when the SoP is in a system level state.

System of package (SoP) module and mobile computing device having the SoP

A package on package may include: a first printed circuit board (PCB); a bottom package which includes a first chip die and a second chip die attached to the first PCB; a top package which includes a second PCB and a third chip die attached to the second PCB, and is overlaid over the bottom package; and/or first stack connection solder balls and second stack connection solder balls which are electrically connected between the first PCB and the second PCB, and are formed only around two sides facing each other among sides of the bottom package.

Package on packages and mobile computing devices having the same

A semiconductor package includes a printed circuit board (PCB), a chip bonded to the PCB, a mold protecting the chip and exposing a backside surface of the chip, via openings extending in the mold to expose first contacts bonded to the PCB, and at least one first marking inscribed in a marking region of the mold between the backside surface of the chip and the vias. The mold has an exposed molded underfill (eMUF) structure covering the sides of the chip while exposing the backside surface of the chip. A PoP package includes a top package stacked on and electrically connected to the semiconductor package.

Semiconductor device having markings and package on package including the same

A semiconductor chip may include a semiconductor substrate, a first central pad, a second central pad, a first peripheral pad, a second peripheral pad, a first pad line and a second pad line. The semiconductor substrate may have an active face. The first central pad and the second central pad may be arranged on a central region of the active face. The first peripheral pad and the second peripheral pad may be arranged on an edge region of the active face. The first pad line may be connected between the first central pad and the first peripheral pad. The second pad line may be connected between the second central pad and the second peripheral pad.

Semiconductor chip, flip chip package and wafer level package including the same

In a bonding configuration for a semiconductor device package, the bonding angles of the bonding wires are maintained within acceptable limits, without causing an increase in the chip die size, and without necessitating the use of the corner rule. In this manner, the occurrence of shorting between adjacent bonding wires can be mitigated or eliminated, and device net die count during fabrication can be increased.

Bonding configurations for lead-frame-based and substrate-based semiconductor packages

A semiconductor wafer includes a plurality of passive device units, which are electrically connected across scribe lines. Passive device chips in the wafer that are adjacent to one another in a first direction are electrically connected in parallel, while passive device units adjacent to one another in a second direction are connected in series. By selecting a number of adjacent passive device units extending in the first and second direction, and separating the selected units from the wafer along the corresponding scribe lines, a passive device chip having a desired electrical characteristic (e.g., capacitance or resistance) can be obtained. Such passive device chips may be assembled in a semiconductor package where they are electrically connected to active devices.

Semiconductor wafer having electrically connected passive device chips, passive devices and semiconductor package using the same

A method for manufacturing a flip chip package includes preparing an IC chip that includes an active surface on which electrode pads are formed, attaching a heat dissipater to a backside of the IC chip with a thermal interface material (TIM), providing a flux filler layer on a substrate, where the substrate includes a plurality of land pads each corresponding to each of the plurality of electrode pads, and mounting the IC chip to the substrate with the active surface facing the substrate. The method further includes forming metal connectors on each of the corresponding plurality of electrode pads of the IC chip, and forming an electrical interconnection between the land pads of the substrate and the plurality of metal connectors by soldering the metal connectors to the land pads. The heat dissipator may be a hermetic heat spreader having a pair of opposite ends bent toward the substrate, which are hermetically sealed to the substrate.

Method for manufacturing flip chip package devices with a heat spreader

In accordance with the present invention, a chip scale package (CSP) is manufactured at wafer-level. The CSP includes a chip, a conductor layer for redistribution of the chip pads of the chip, one or two insulation layers and multiple bumps, which are interconnected to respective chip pads by the conductor layer and are the terminals of the CSP. In addition, in order to improve the reliability of the CSP, a reinforcing layer, an edge protection layer and a chip protection layer are provided. The reinforcing layer absorbs stress applied to the bumps when the CSP is mounted on a circuit board and used for an extended period, and extends the life of the bumps, and thus, the life of the CSP. The edge protection layer and the chip protection layer prevent external force from damaging the CSP. After forming all elements constituting the CSP on the semiconductor wafer, the semiconductor wafer is sawed to produce individual CSPs.

Chip scale packages manufactured at wafer level

A semiconductor package includes: a substrate having an upper surface and a lower surface; an integrated circuit chip having bond pads; a lid attached on the upper surface of the substrate so as to cover the chip; and one or more projections that electrically connect the lid to a plurality of ground patterns. The substrate has substrate pads formed on the upper surface, and one or more of the substrate pads extend to form the ground patterns. The chip is bonded on the upper surface of the substrate. One or more of the bond pads are ground bond pads, and the bond pads are electrically connected to the corresponding substrate pads. An electrically nonconductive adhesive is used for the attachment of the lid to the substrate, and the projections are connected to the ground patterns by an electrically conductive adhesive. The ground projections are positioned at four corners of a cavity that is formed between the substrate and the lid. The semiconductor package further includes: external connection terminals formed on the lower surface of the substrate and electrically connected to the corresponding substrate pads; and a thermal interface material is interposed between lid and the chip, the thermal interface material transmitting heat generated by the chip to the lid.

Semiconductor package with ground projections

In accordance with the present invention, a chip scale package (CSP) is manufactured at wafer-level. The CSP includes a chip, a conductor layer for redistribution of the chip pads of the chip, one or two insulation layers and multiple bumps, which are interconnected to respective chip pads by the conductor layer and are the terminals of the CSP. In addition, in order to improve the reliability of the CSP, a reinforcing layer, an edge protection layer and a chip protection layer is provided. The reinforcing layer absorbs stress applied to the bumps when the CSP are mounted on a circuit board and used for an extended period, and extends the life of the bumps, and thus, the life of the CSP. The edge protection layer and the chip protection layer prevent external force from damaging the CSP. After forming all elements constituting the CSP on the semiconductor wafer, the semiconductor wafer is sawed to produce individual CSPs.

Chip scale packages and methods for manufacturing the chip scale packages at wafer level

A semiconductor lead frame is disclosed to improve the characteristics and reliability of a semiconductor device using lines of bonding pads in a cross-arrangement. The semiconductor lead frame comprises a rectangular semiconductor chip with a plurality of output terminals of associated circuits, a plurality of leads having inner and outer ends, bus bars extending around the inner ends of the leads, at least one insulator disposed between the semiconductor chip and the inner ends of the leads for electrically insulating the chip and the leads, metal wires electrically connecting the inner ends of the leads to selected and respective bonding pads and the bus bars to the pads in common. The leads are inclined relative to the lines of pads to form a line of outer terminals for the lead frame which extend over a distance exceeding the length of the chip. The semiconductor device can thereby accommodate a great number of bonding pads in response to the high density demand without increasing the size of the chip.

Growing community of inventors

Seongnam-si, South Korea

Heung Kyu Kwon