Samsung Electronics Co., Ltd.

Heung-Bae Lee

Hee-Mun Bang

Jin-Soo Park

Jung-Eun Lee

Jungho Lee

Tae-Wook Kim

Chang-sik Yoo

Young-eil Kim

Choong-yul Cha

Jung-ho Lee

Yun-seong Eo

Si-Gyoung Koo

Ick-jin Kwon

Kyu-don Choi

Jae-woo Park

A track-and-hold circuit includes a bootstrapped clock generator and a track-and-hold unit. The bootstrapped clock generator receives an input voltage signal and generates a sampling control signal having a voltage level lower than or equal to a level of a power supply voltage by maintaining an initial level of a boost capacitor voltage at a level lower than the level of the power supply voltage. The boost capacitor voltage is a voltage that is charged across a boost capacitor included in the bootstrapped clock generator and the sampling control signal is generated based on a clock signal. The track-and-hold unit samples and holds the input voltage signal in response to the sampling control signal to generate a sampled signal.

Bootstrapped clock generator and track-and-hold circuit including the same

A folding analog-to-digital converter including: a reference voltage generator, a track-and-hold circuit and a first pre-amplification circuit. The reference voltage generator generates a plurality of reference voltages. The track-and-hold circuit generates a sampling control signal having a voltage level lower than or equal to a level of a power supply voltage by maintaining an initial level of a boost capacitor voltage at a level lower than a level of a power supply voltage, and samples and holds an input voltage signal in response to the generated sampling control signal to generate a sampled signal. The first pre-amplification circuit amplifies each of voltage differences between the sampled signal and each of the plurality of reference voltages.

Folding analog-to-digital converter

A digital phase detector includes a quantization unit that quantizes a frequency of a reference signal to generate reference delay information and reference integer phase information, and quantizes a frequency of an oscillation signal to generate oscillation delay information and oscillation integer phase information. A first conversion unit converts the frequency of the reference signal into reference frequency information based upon the reference delay information and the reference integer phase information. A second conversion unit converts the frequency of the oscillation signal into oscillation frequency information based upon the oscillation delay information and the oscillation integer phase information. A calculation unit converts the reference frequency information and the oscillation frequency information into first and second phase information, respectively, and outputs a digital phase difference between the first phase information and the second phase information.

Digital phase detector, and digital phase locked loop including the same

A radio frequency identification (RFID) reader is provided, having a transmitting circuit that generates a transmitted signal to operate an RFID tag, a receiving circuit that receives a received signal including a tag signal from the RFID tag and a transmission carrier leakage signal leaking from the transmitting circuit, and a leakage removing circuit that senses a phase and amplitude of the transmission carrier leakage signal inputted to the receiving circuit, converts the transmitted signal from the transmitting circuit into a signal having a phase opposite to that of the transmission carrier leakage signal and an amplitude equal to that of the transmission carrier leakage signal, and synthesizes the converted signal and the received signal inputted to the receiving circuit.

RFID reader and method for removing a transmission carrier leakage signal

A communication apparatus and a low noise amplifying method. The communication apparatus includes a gain adjusting unit to adjust a gain of an input signal; a combiner to generate an output signal using the signal gain-adjusted at the gain adjusting unit; and a feedback unit which provides a feedback signal, which is generated using the output signal generated at the combiner, to an input stage. Accordingly, various frequency bands defined in the wireless standards can be supported. Since the load impedance is generated without resistance, the manufacturing cost and the product size can be reduced.

Communication apparatus and low noise amplifying method

A radio frequency (RF) filter is provided which includes a band pass filter unit and an amplifying unit. If a signal having a frequency in a first band is input, the RF filter performs band pass filtering, and if a signal having a frequency in a second band is input, the RF filter performs an amplifying process. The RF filter can be used for various RF signal processing devices, such as digital broadcast receiving tuners.

RF filter and digital broadcast receiving tuner and RF signal processing device using RF filter

A data slice circuit to separate data carried on a video signal only at a line on which the data is carried and a method thereof. The circuit includes a top peak detector to detect a top peak of an input video signal to generate a top peak detection signal and a bottom peak detector to detect a bottom peak of the video signal to generate a bottom peak detection signal. A composite synchronous signal separation circuit separates a composite synchronous signal from the video signal, and a clock run-in window circuit generates a first control signal for a clock run-in interval. A sampling/holding circuit samples an intermediate value between the top peak detection signal and the bottom peak detection signal in response to the first control signal of a first state, and holds the sampled intermediate value to generate a reference voltage in response to the first control signal of a second state. A second control signal generator receiving the composite synchronous signal generates a second control signal indicating a line on which data is carried, and a comparator circuit compares the video signal with the reference signal in response to the second control signal. Therefore, the data slice circuit performs a data slice operation only at the line on which the data is carried.

Data slice circuit for slicing data carried on a video signal and a method thereof

An automatic fine tuning (AFT) circuit used for processing an image intermediate frequency signal for a video display device. The AFT circuit, which produces an automatic fine tuning signal, by which an image intermediate frequency signal maintains a constant carrier center frequency, includes a phase shift device for performing a phase shift of 90.degree. in the state of the constant carrier center frequency, a control current generating device for generating a control current in response to a variation of a variable resistor value, a resonant frequency variable device for varying a resonant frequency of the resonance circuit, by varying a capacitance to be resonated by the control current, and a phase detecting device for multiplying the image intermediate frequency signal by a phase-shifted image intermediate frequency signal, and for generating the automatic fine tuning signal. According to one aspect of the AFT circuit, the phase shift device includes a resonance circuit for performing the phase shift in relation to the image intermediate frequency signal.

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Seongnam-si, South Korea

Heung-Bae Lee