Samsung Electronics Co., Ltd.

Heui-Seog Kim

Jong-Keun Jeon

Wha-Su Sin

Seok-Young Yoon

Jae-Hong Kim

Jung-Hyun Park

Jun-Young Ko

Jae-Yong Park

Dae-Sang Chan

Hyeck-Jin Jeong

Yean-Sang You

Dae-Sang Chun

Hyeck-Jin Joung

Soo-Tae Chae

A semiconductor package and a method of manufacturing the package are provided. The semiconductor package comprises: a mounting substrate including a bond finger; at least one semiconductor chip disposed on the mounting substrate, the semiconductor chip including a bonding pad; a first molding member disposed on the mounting substrate so as to cover the bond finger and the bonding pad, the first molding member including an interconnection path disposed inside the first molding member so as to connect the bond finger to the bonding pad; a conductive element disposed in the interconnection path; and a second molding member overlying the first molding member. The interconnection path can be formed by a laser process. The conductive element can be formed by conductive nanoparticles or metal wires.

Semiconductor package and method of manufacturing the semiconductor package

An inexpensive method of manufacturing a semiconductor package using a redistribution substrate that is relatively thin. The method includes: attaching a semiconductor chip to a redistribution substrate; attaching the redistribution substrate to which the semiconductor chip is attached to a printed circuit board; removing a support substrate of the redistribution substrate; forming via holes to expose a bond pad of the semiconductor chip and a bond finger of the printed circuit board; and filling the via holes with a conductive material. Meanwhile, a redistribution substrate to which at least one other semiconductor chip may be mounted on the redistribution substrate.

Method of manufacturing semiconductor package using redistribution substrate

A method of processing a semiconductor wafer that has a first surface and a second surface opposite to the first surface. The method includes forming grooves of a predetermined depth on the second surface on which circuit patterns are formed, attaching a first surface of a protective tape to the second surface on which the grooves are formed, attaching a carrier tape to a second surface of the protective tape opposite to the first surface of the protective tape so that the first surface of the semiconductor wafer can be oriented upward, removing the first surface of the semiconductor wafer by a predetermined thickness and dividing the semiconductor wafer into chips by the grooves, and supplying each chip to a die bonder in the state where the first surface of the of the chip is oriented upward. Only one kind of die bonder is needed. A UV-type tape is not required.

Method of processing a semiconductor wafer for manufacture of semiconductor device

A POGO pin that can measure low frequency products as well as RF products and also have a long life span, and a test socket including the POGO pin are provided. The POGO pin includes a metal plunger formed of a conductive metal so as to electrically contact the semiconductor package, and a rubber contact pin connected with the metal plunger and formed of a conductive rubber so as to electrically contact the test board.

POGO pin and test socket including the same

The present invention relates to an insert block for testing semiconductor devices. The insert block comprises one or more pushers, installed in a block body having a loading space to accommodate a semiconductor device under test, including a first push rod to apply force to one of adjacent sides of the semiconductor device under test and a second push rod to apply force to the other thereof. Accordingly, firm centering of semiconductor devices under test relative to the contact pins of the test socket along the two perpendicular axes (for instance, x and y axes) on the top or bottom surface of the semiconductor device is achieved and leads to the proper interfaces between the external terminals of the semiconductor device under test and the contact pins of the test socket, and thereby improves the quality of connection therebetween.

Insert block with pusher to push semiconductor device under test

An integrated management system is provided for automatically executing a procedure of reviewing and editing an assembly reference and a bonding specification used for manufacturing IC packages. The system includes a drawing management system (DMS) that creates the assembly reference, and a bonding specification drawing system that creates, based on the assembly reference, the bonding specification. The integrated management system further includes a DMS database server that stores and manages the assembly reference and the bonding specification, a DMS file server that manages a blank diagram, a package outline, a bonding diagram, and a standard file, and a DMS web server that provides a web interface to a user for permitting a remote access. In particular, the drawing management system has a bonding rule check module that verifies whether the bonding specification meets a bonding rule suitable for an automated wire bonding process. The drawing management system produces the standard file to be transmitted to bonding equipments.

Growing community of inventors

Chungcheongnam-do, South Korea

Heui-Seog Kim