Arm Limited

Hetansh Pareshbhai Shah

Bo Zheng

Lalit Gupta

Nimish Sharma

Fakhruddin Ali Bohra

El Mehdi Boujamaa

Nicolaas Klarinus Johannes Van Winkelhoff

In a particular implementation, a circuit comprises: a memory array including a plurality of bit cells, where each of the bit cells are coupled to a respective bit path; a first multiplexer comprising a plurality of column address locations, where each of the plurality of column address locations is coupled to the memory array and corresponds to a respective bit path capacitance; and a variable capacitance circuit coupled to a reference path and configured to substantially match reference path capacitance to each of the respective bit path capacitances.

Circuits and methods for capacitor modulation

Various implementations described herein are directed to a device having memory circuitry with a core array of bitcells. The device may include write assist circuitry having passgates coupled to the bitcells via bitlines. The passgates may include a first passgate coupled to the bitcells via a first bitline and a second passgate coupled to the bitcells via a second bitline, and a gate of the second passgate may be coupled to the first bitline.

Write assist circuitry

Growing community of inventors

Ahmedabad, India

Hetansh Pareshbhai Shah