Samsung Electronics Co., Ltd.

Hgst Netherlands, B.v.

Hessam Mahdavifar

Mostafa El-Khamy

Jungwon Lee

Inyup Kang

Zvonimir Z Bandic

Luiz M Franca-Neto

Cyril Guyot

Robert Eugeniu Mateescu

Qingbo Wang

Gennady Feygin

An apparatus and a method. The apparatus includes a plurality of polarization processors, including n inputs and n outputs, where n is an integer, wherein the plurality of polarization processors is configured to polarize channels with different bit-channel reliability; and at least one permutation processor, including n inputs and n outputs, wherein each of the at least one permutation processor is connected between two of the plurality of polarization processors, and connects the n outputs of a first of the two of the plurality of polarizations processors to the n inputs of a second of the two of the plurality of polarization processors between which each of the at least one permutation processor is connected in a permutation pattern, wherein at least one permutation processor is configured to not further polarize a bit channel.

System and method for maximal code polarization

An apparatus and a method. The apparatus includes a plurality of polarization processors, including n inputs and n outputs, where n is an integer; and at least one permutation processor, including n inputs and n outputs, wherein each of the at least one permutation processor is connected between two of the plurality of polarization processors, and connects the n outputs of a first of the two of the plurality of polarizations processors to the n inputs of a second of the two of the plurality of polarization processors between which each of the at least one permutation processor is connected in a permutation pattern that maximally polarizes the n outputs of the second of the two of the plurality of polarization processors.

A computing system includes: an inter-device interface configured to communicate content; and a communication unit, coupled to the inter-device interface, configured to process the content based on a polar communication mechanism utilizing multiple processing dimensions for communicating the content, including: generating a node result with a first orthogonal mechanism, and processing the node result from the first orthogonal mechanism with a second orthogonal mechanism.

Computing system with polar processing mechanism and method of operation thereof

A computing system includes: a communication unit configured to: determine a relaxed coding profile including a polar-processing range for processing content data over a bit channel; process the content data based on a total polarization level being within the polar-processing range, the polar-processing range for controlling a polar processing mechanism or a portion therein corresponding to the bit channel for the content data; and an inter-device interface, coupled to the communication unit, configured to communicate the content data.

System and method for encoding and decoding of data with channel polarization mechanism

An apparatus and method of constructing a universal polar code is provided. The apparatus includes a first function block configured to polarize and degrade a class of channels Wto determine a probability of error Pof each bit-channel of W, wherein j&#x3b5;{1, 2, . . . , s}, in accordance with a bit-channel index i; a second function block configured to determine a probability of error Pfor the universal polar code for each bit-channel index i; a third function block configured to sort the P; and a fourth function block configured to determine a largest number k of bit-channels such that a sum of corresponding k bit-channel error probabilities Pis less than or equal to a target frame error rate Pfor the universal polar code, wherein the indices corresponding to the k smallest Pare good bit-channels for the universal polar code.

Apparatus and method of constructing polar code

A computing system includes: an interface configured to communicate a coordination profile for coordinating a second transmitter device with a first transmitter device; and a unit, coupled to the interface, configured to generate a first encoded message using a message polarization mechanism based on the coordination profile for coordinating the first encoded message with a second encoded message concurrently transmitting through the second transmitter device. A further embodiment of the computing system includes: an interface configured to communicate a receiver signal for representing a first encoded message and a second encoded message coordinated for concurrent transmission; a unit, coupled to the interface, configured to: determine a communication rate associated with the receiver signal, and decode the receiver signal based on a message polarization mechanism and the communication rate for identifying the first encoded message based on a coordination profile corresponding to the communication rate.

Computing system with coordinated multiple-access mechanism and method of operation thereof

A concatenated encoder is provided that includes an outer encoder, a symbol interleaver and a polar inner encoder. The outer encoder is configured to encode a data stream using an outer code to generate outer codewords. The symbol interleaver is configured to interleave symbols of the outer codewords and generate a binary stream. The polar inner encoder is configured to encode the binary stream using a polar inner code to generate an encoded stream. A concatenated decoder is provided that includes a polar inner decoder, a symbol de-interleaver and an outer decoder. The polar inner decoder is configured to decode an encoded stream using a polar inner code to generate a binary stream. The symbol de-interleaver is configured to de-interleave symbols in the binary stream to generate outer codewords. The outer decoder is configured to decode the outer codewords using an outer code to generate a decoded stream.

Method and system for encoding and decoding data using concatenated polar codes

A data storage system includes a memory circuit that has memory cells and a control circuit that is operable to receive data bits provided for storage in the memory cells. The control circuit is operable to receive a first matrix. Each row of the first matrix corresponds to a unique one of the data bits. The control circuit is operable to generate a second matrix having only the rows of the first matrix that correspond to the data bits provided for storage in a subset of the memory cells having stuck-at faults. The control circuit is operable to generate a third matrix having linearly independent columns of the second matrix. The control circuit is operable to encode the data bits to generate encoded data bits and redundant bits using the third matrix.

Encoding and decoding data to accommodate memory cells having stuck-at faults

A communication system includes: an antenna for receiving a receiver signal for communicating a transmitter signal corresponding to the receiver signal over transmission channels according to a polar coding scheme; a communication unit including: an arrangement module for generating a sequenced-signal based on the receiver signal according to a permutation mechanism; and a decoder module for determining a communication content based on the sequenced-signal for communicating the communication content intended by the transmitter signal with a device. The communication system includes: a communication unit including an encoder module for determining a coded-message for representing a communication content according to a polar coding scheme, permutation module for generating a message-channel map for mapping the coded-message to transmission channels; and an antenna for transmitting a transmitter signal based on the coded-message according to the message-channel map for communicating the transmitter signal through the transmission channels with a device.

Communication system with compound coding mechanism and method of operation thereof

A data storage system has a memory circuit that comprises memory cells and a control circuit that receives data bits provided for storage in the memory cells. The control circuit encodes the data bits to generate a first set of redundant bits and encoded data bits, such that the encoded data bits selected for storage in a first subset of the memory cells with first stuck-at faults have digital values of corresponding ones of the first stuck-at faults. The control circuit encodes the first set of redundant bits to generate a second set of redundant bits. The control circuit performs logic functions on the second set of redundant bits and the encoded data bits to generate a third set of redundant bits, such that redundant bits in the third set of redundant bits selected for storage in a second subset of the memory cells with second stuck-at faults have digital values of corresponding ones of the second stuck-at faults.

Encoding and decoding redundant bits to accommodate memory cells having stuck-at faults

A data storage system includes a memory circuit having memory cells and a control circuit. The control circuit is operable to receive data bits provided for storage in the memory cells. A subset of the memory cells have predetermined stuck-at faults. The control circuit is operable to compute a binomial coefficient for each of the predetermined stuck-at faults based on a bit position of a corresponding one of the predetermined stuck-at faults within the memory cells. The control circuit is operable to add together the binomial coefficients to generate an encoded number using a combinatorial number system. The control circuit is operable to generate a first set of redundant bits that indicate the encoded number. The first set of redundant bits are used to decode bits read from the memory cells to regenerate the data bits.

Techniques for encoding and decoding using a combinatorial number system

A data storage system includes a memory circuit and a control circuit. The control circuit is operable to receive data bits provided for storage in memory cells of the memory circuit. The control circuit is operable to compare each of the data bits provided for storage in a corresponding one of the memory cells having a stuck-at fault to a value of the stuck-at fault, and to invert each of the data bits having a different value than the value of the stuck-at fault of the corresponding one of the memory cells to generate encoded data bits. The control circuit is operable to generate redundant bits that indicate the encoded data bits to invert to regenerate the data bits.

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San Diego, CA, United States of America

Hessam Mahdavifar