Infineon Technologies Ag

Infineon Technologies Austria Ag

Infineon Technologies Dresden Gmbh & Co . Kg

Herwig Wappis

Peter Bogner

Peter Singerl

David Seebacher

Gerhard Maderbacher

Pantelis Sarais

Jens Barrenscheen

Juergen Schaefer

Fabrizio Cortigiani

Rolf Weis

Kennith Kin Leong

Christoph Sandner

Martin Mataln

Ralf Rudolf

Martin Pernull

David Astrom

Clemens Roessler

Johannes Janschitz

Clifford Fyvie

Niranjan Reddy Suravarapu

Andreas Fugger

Massimo Rigo

Michael Sieberer

A circuit for biasing a transistor is provided. The circuit includes an output terminal configured to be coupled to a gate terminal of the transistor and circuitry. In a first state, the circuitry is configured to output a control signal at a first voltage level for setting the transistor to a first transistor state. In a second state, the circuitry is configured to first output the control signal at a second voltage level different from the first voltage level following by changing the control signal from the second voltage level towards a third voltage level different from the first and second voltage level over time.

Circuit and method for biasing a transistor and corresponding device

A device for controlling trapped ions includes an ion trap, a plurality of field electrodes configured to control ions in the ion trap, and a controller chip. The controller chip includes at least one delta-sigma digital to analog converter (DS-DAC) module including a DS-DAC circuit configured to receive a digital data stream, convert the digital data stream to analog control voltages, and supply the analog control voltages to the field electrodes.

Device for controlling trapped ions and including a delta/sigma dac module

A semiconductor device includes: a semiconductor body having an active region and a substrate region beneath the active region; a bidirectional switch having first and second gate structures configured to control a conductive state of a channel in the active region, and first and second input-output terminals electrically connected to the channel; and a passive discharge circuit in parallel with the bidirectional switch and configured to utilize a fraction of a voltage across the first and second input-output terminals to switch on a transistor device that electrically connects the substrate region to the input-output terminal at the lower potential during an off-state of the bidirectional switch and during ZVS (zero-voltage switching) transition periods.

Passive discharge circuit for bidirectional semiconductor switches

Sampling circuits and methods for sampling are provided. In a first operating phase, sampling capacitors are coupled to inputs, and in a second operating phase, to a common-mode signal.

Sampling circuit and sampling method

In some examples, an integrated circuit device includes a sampling switch configured to sample an input signal. The integrated circuit device also includes a first evaluation unit configured to receive the sampled input signal from the sampling switch and evaluate the sampled input signal. The integrated circuit device further includes a second evaluation unit configured to receive the sampled input signal from the sampling switch and evaluate the sampled input signal. The sampling switch is configured to deliver the sampled input signal to the first evaluation unit and deliver the sampled input signal to the second evaluation unit.

Using a sampling switch for multiple evaluation units

Devices and methods for generating a bias voltage for a transceiver operating in time division multiplexing operation, and corresponding transceivers are provided. In this case, the bias voltage is controlled in guard intervals between transmission and reception of signals by the transceiver.

Method and device for providing a bias voltage in transceivers operating in time division multiplexing operation

A circuit having capacitors, and corresponding method. A circuit and corresponding methods are provided. A controller causes a first capacitor to be connected to an input connection in a first operating phase, charge to be transferred from the first capacitor to a second capacitor in a second operating phase and charge to be transferred from the second capacitor to a processing circuit in a third operating phase. The input connection and the second capacitor belong to different voltage domains.

Circuit with capacitors and corresponding method

Method and device for providing a bias voltage in transceivers

In one example, a method includes outputting, by a power supply and across a supply node and a ground node, a supply power signal; and selectively outputting, by a driver, a power signal to a second terminal of a light emitting element that has a first terminal and the second terminal, wherein the first terminal of the light emitting element is coupled to a load node, wherein a supply terminal of the driver is coupled to the supply node, wherein a ground terminal driver is coupled to the ground node, and wherein a difference between a potential of the supply node and a potential of the ground node is less than an activation voltage of the light emitting element.

Driving light emitting elements with reduced voltage drivers

Sigma-delta converters having a sampling circuit are provided. The sampling circuit is actuated such that sampling times are at least partially random.

Sigma-delta converters and corresponding methods

An electronic circuit includes: a drive circuit having an output coupled to a control node of a first electronic switch; a switch circuit with second electronic switches, load paths of the second electronic switches being connected in series, and the switch circuit being connected between a first load node of the first electronic switch and a reference node; and a level shifter coupled between a first signal input and an input of the drive circuit and including cascaded level shifter cells. Each level shifter cell includes a signal input and output, and first and second supply nodes. Each level shifter cell is associated with a respective second electronic switch. The first supply node of each level shifter cell is coupled to a first load node of the associated second electronic switch, and the second supply node is coupled to a second load node of the associated second electronic switch.

Electronic circuit with several electronic switches connected in series and a drive circuit

A switching circuitry is configured to provide, during an ON-State, a connection between a first port and second port and to electrically disconnect, during an OFF-State, the first port from the second port. The switching interface comprises a first and a second cascode transistor element having an applicable operational voltage and comprising a control terminal, wherein the first cascode transistor element is connected with the first port of the switching interface and wherein the second cascode transistor element is connected with the second port of the switching interface. The switching interface comprises a switching transistor element, having the applicable operational voltage and comprising a third control terminal, the switching transistor element being serially connected the first and second cascode transistor elements. A supply signal arrangement is connected to the control terminals and configured to provide control voltages to the control terminals.

Switching circuitry, DC-interface and method for operating a switching circuitry

Techniques are provided for adapting a bias provided to a radio frequency (RF) power amplifier (PA), so as to achieve linear operation over a wide range of conditions. The techniques use open-loop temperature compensation based upon a sensed current during periods when the RF PA is active and inactive. A closed-loop control technique is enabled when the RF PA is inactive. The combined control techniques compensate for temperature variation as well as long-term drift of the semiconductor properties of the devices within the RF PA.

Adaptive biasing control for radio frequency power amplifiers

Disclosed herein are embodiments of a precharge sample-and-hold circuit. The circuit has an input terminal, a reference voltage terminal and an output terminal. Further, the circuit has a sampling capacitance coupled between the input terminal and the reference voltage terminal and configured to provide the sample voltage when said sample-and-hold circuit is in a holding mode and a cancellation capacitance. Implementations of a precharge sample-and-hold circuit and of methods to operate a precharge sample-and-hold circuit in an analog/digital converter are also disclosed.

Growing community of inventors

Drobollach, Austria

Herwig Wappis