Intel Corporation

Herve R Lambert

Amar A Ghori

Joseph R Bond

Steven M McIntyre

An integrated circuit microcontroller with improved system bus timing modes that allow higher speed operation when accessing external memory. The improved system bus timing modes are generated by using the edges of a higher frequency secondary clock to trigger system bus timing events instead of using the edges of the phase clock. This can be done without major redesign using combinational logic because the phase clock and the higher frequency secondary clock are substantially in-phase.

Microcontroller having selectable bus timing modes based on primary and

Methods and circuitry for sharing a memory space of a microcontroller with a processor. The memory space corresponds to a random access memory accessible by the microcontroller. The memory space includes random access memory on a same substrate as the microcontroller. The processor is located on a different substrate from the microcontroller. The circuitry includes a slave port for communicating data between the processor and the microcontroller. The slave port receives a logical address and a control signal from the processor. The slave port generates an interrupt signal in response to the control signal. An interrupt server generates memory control signals in response to the interrupt signal. A memory controller reads data from and writes data to the slave port and a memory location associated with the logical address in response to the memory control signals.

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Gilbert, AZ, United States of America

Herve R Lambert