Nxp B.v.

St-ericsson Sa

Integrated Device Technology, Inc.

Herve Marie

Lionel Guiraud

Yann Le Guillou

Nguyen Trieu Luan Le

Arnaud Biallais

Sofiane Ellouz

Mickael Lucas

Denis Crespo

Guillaume Herault

In one aspect, a buffer circuit comprises a source or emitter follower input stage and output stage. A load is provided between the stages which comprises a representation of an output load of the buffer circuit. This improves the circuit linearity whilst enabling a high input impedance to be obtained. In another aspect, a buffer circuit comprises a source or emitter follower output stage. A load is in the form of a filter is provided and which comprises a representation of an output load of the buffer circuit.

Source or emitter follower buffer circuit and method with mirrored current

Source or emitter follower buffer circuit and method

Embodiments of a pipeline analog-to-digital converter is provided. In accordance with some embodiments, a pipeline analog-to-digital converter includes a stage, the stage including a residue amplifier that amplifies a residual voltage generated by the stage to obtain an amplified residual voltage; a backend digitizer that digitizes the amplified residual voltage to generate a digitized residual; and a digital correction circuit that corrects the digitized residual according to which zone the digitized residual is found.

Digital extraction and correction of the linearity of a residue amplifier in a pipeline ADC

A protection circuit () is disclosed for protecting an integrated circuit having a first supply rail (Vcc) and a second supply rail (Vss) from exposure to an excessive voltage. The protection circuit () comprises a sensor () for sensing a voltage increase on the first supply rail (Vcc). Such a sensor may be implemented as an RC element. The sensor () has an output coupled to a signal path for providing a detection signal on said path. The sensor () triggers a clamping circuit () to clamp the first supply rail (Vcc) to the second supply rail (Vss) in response to the detection signal, which typically signals an ESD event on the supply rails. A pre-amplifying stage () is coupled between the sensor () and the clamping circuit () to amplify the detection signal for the clamping circuit (). The protection circuit further comprises a hold circuit () for holding the control input of the pre-amplifying stage () in an enabled state upon termination of the detection signal. Such a hold circuit may comprise a further RC element for accelerating the activation of the clamping circuit () and extending the activation of the clamping circuit beyond the termination of the detection signal, thus yielding a more efficient protection circuit ().

Voltage surge protection circuit

A digitally controlled variable capacitance integrated electronic circuit module () comprises a set of basic cells in a matrix arrangement. Each basic cell itself comprises a functional block () which can be switched between two individual capacitance values, a control block (), and a control junction connecting the control block and the functional block of said basic cell. The functional blocks and the control blocks are grouped into separate regions () of the matrix arrangement, to reduce capacitive interaction between output paths and power supply paths of the module. The functional blocks can still be switched in a winding path order within the matrix arrangement. A module of the invention can be used in an oscillator capable of producing a signal at 4 GHz.

Variable capacitance integrated electronic circuit module

A circuit arrangement is described comprising a first receiver configured to receive a first input signal, a second receiver configured to receive a second input signal, a first signal generator configured to generate a first pulse signal, a second signal generator configured to generate a second pulse signal, wherein a delay between a rising edge of the first pulse signal and a rising edge of the second pulse signal is proportional to a difference between the first input signal and the second input signal, a first converter configured to convert the first pulse signal to a first digital number proportional to a width of the first pulse signal, a second converter configured to convert the second pulse signal to a second digital number proportional to a width of the second pulse signal, wherein at least one of the first converter and the second converter comprises a cascade of at least two converter stages, wherein each converter stage of the at least two converter stages is configured to propagate and shrink the respective pulse signal. Also a corresponding method is described.

Phase frequency to digital converter

A method for controlling a modulation signal for modulating a phase locked loop. A scaling control signal for scaling the modulation signal is generated using the error signal of the phase locked loop. The scaling control signal is adjusted when the modulation signal and the phase of the modulation signal have the same sign.

Phase locked loop calibration

A wafer comprises i) at least one independent die having internal integrated components, a multiplicity of internal pads connected to some of the internal integrated components, ii) scribe lanes defined between and around each independent die, and in part of which are defined, for each die, at least a first group of external pads and/or a second group of external test integrated components. The external pads of each first group are connected, through conductive tracks, to a chosen one of the internal pads and/or internal integrated components of the associated die, and arranged to be fed with chosen test signals or to collect test result signals. Each external test integrated components of each second group is connected, through conductive tracks, to a chosen one of the die internal pads and/or die internal integrated components and/or to external pads of a first group.

Wafer with scribe lanes comprising external pads and/or active circuits for die testing

An analog-to-digital converter (ADC) of the Sigma Delta type provides a stream of digital output samples (OUT) in response to an analog input signal (IN). The analog-to-digital converter (ADC) comprises a quantizer (QNT) that has a dead zone. The quantizer (QNT) provides a digital output sample that has a neutral value when the quantizer (QNT) receives an input signal whose amplitude is within the dead zone. A feedback path (DAC) within the analog-to-digital converter (ADC) provides a feedback action only in response to a digital output sample that has a value other than the neutral value.

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Ver sur Mer, France

Herve Marie