Cypress Semiconductor Corporation

Herve LeTourneur

Hans Van Antwerpen

Dinesh Maheshwari

Cathal G Phelan

Gaurav Singh

Donald W Smith

Dinesh Ramanathan

Alakesh Chetia

Manoj Gujral

An example method and system process a SuperSpeed packet transferred at a SuperSpeed transfer rate and based on processing the SuperSpeed packet, generate a Universal Serial Bus (USB) 2.0 packet to be transferred at a USB 2.0 transfer rate, the USB 2.0 transfer rate being less than the SuperSpeed transfer rate.

Systems and methods for super speed packet transfer

At least one downstream interface may be configured to be simultaneously connected to both a USB 3.0 compliant device and a USB 2.0 compliant device. The interface may be used for communicating with a USB 3.0 compliant device via a downstream port and simultaneously communicating with a USB 2.0 compliant device via the downstream port.

Downstream interface ports for connecting to USB capable devices

A multiple master USB hub device and method for enabling multiple OTG and host devices to control peripherals and slave devices with a connection of the multiple OTG and host devices to the USB hub device. The multiple master USB hub device is configured to enable at least two USB devices connected thereto to each be configured as host/master elements to control OTG and peripheral/slave devices connected to the USB hub device, the USB hub device comprising an element configured to switch configuration of each of the at least two USB devices to a host/master configuration at different predetermined times.

Operation of multiple masters/hosts through a hub

USB port connected to multiple USB compliant devices

A device may include a first data path coupled between a first port and a data transfer section that enables data paths between the first data path and at least a second port and a third port. A second data path may be coupled between the first port and the second port that bypasses the data transfer section and is not coupled to the second or third ports.

Signal connection device and method

A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

Growing community of inventors

Mountain View, CA, United States of America

Herve LeTourneur