International Business Machines Corporation

Herve L Beranger

Armand Brunin

Jean-Paul Rousseau

Gene J Gaudenzi

Helmut Schettler

Dominique M Omet

Stuart D Rapoport

Dennis C Reedy

Jean-Luc Peter

Bruno Caplier

Claude Marzin

Frederic Joly

A fast high-density data compression circuit adapted to semiconductor integrated circuits of the memory type including an ABIST unit. This circuit, which compares the data-out signals output by the memory unit with the expected data generated by the ABIST unit to deliver a signal on a cycle by cycle basis, which is indicative of the fail/no fail status of the memory unit.

Fast data compression circuit for semiconductor memory chips including

A logic circuit family derived from the conventional 2 level single-ended cascode logic circuit. The basic logic circuit performing a 2--2 OA/AI logic function shown in the attached drawing is given for illustration purposes. It comprises: a logic tree 35 comprised of top and bottom stages 37, 36 dotted at the tree output 38 to perform a determined logic function; the top stage 37 includes a current switch comprised of two input transistors TX34, TX35 connected in a differential amplifier configuration with a reference transistor TX36. The bases of input transistors TX34, TX35 are provided with at least two level shifter devices. Preferably, input level shifter devices are Schottky diodes P31, . . . which move the voltages towards the more positive voltage VPP, to add an AND function on each of these input transistors.

Cascode logic circuit including a positive level shift at the input of

A small signal swing line driver, that generates a reduced amount of switching noise and also suppresses transients appearing on the line, is described. Specifically, the driver includes a clamp connected to the driver output to limit the maximum DC driver output level and to suppress voltage transients, e.g. reflections, spikes or the like, appearing on the driven line and caused by conditions external to the driver. The driver also contains circuitry to limit the transition times of the rising and falling edges of the driver output signal in order to reduce the amount of switching noise which is generated by the driver and thereafter coupled onto quiet lines.

Small signal swing driver circuit

A latch that can serve as a bit storage cell in a random-access store. The latch includes an AND gate (diodes D1 and D2) the input IN of which receives the bit to be stored and the other input of which is connected to a write control line WRL. When no write operation is being performed, transistor T1 is turned off and the state of transistor T2 is dependent on output potential OUT. To perform a write operation, line WRL is activated (goes high) and the state of transistor T3 will depend on the value of the bit applied to input IN. Read operations are performed by means of another AND gate (diodes D4 and D5) and an emitter follower (transistor T4) connected via a bit line BL to an output circuit 2. By adding input transistors and emitter followers to the latch, a multi-port storage can be realized, several rows of which can be simultaneously written into and/or read out.

Latch for storing a data bit and a store incorporating said latch

An Exclusive OR circuit with at least two inputs (1 and 2) which exhibits a good immunity to noise. The circuit comprises diodes (D1 and D2) and two transistors (T1 and T2) which have their emitters connected to a reference voltage VR and produce AB at C1. Transistors (T 14 and T5) produce AB at C2, and output transistors (T13 and T6) produce ##STR1## at 3. This circuit can advantageously be used to realize a parity checking circuit.

Exclusive or circuit and parity checking circuit incorporating the same

A power-supply system for use in a monolithic memory characterized in that the power dissipation of the memory is reduced. Each word line is connected to a current switch circuit comprised of a first transistor the collector of which is connected to a voltage V1, its base being connected to the output of the address decoder, a second transistor the collector of which is connected to a voltage V2. V3 being the second voltage impressed on the memory cells (where .vertline.V2.vertline. is larger in magnitude than .vertline.V1.vertline. and .vertline.V3.vertline. is larger in magnitude than .vertline.V2.vertline.). The emitters are connected to each other and to the corresponding word line. According to the state of the decoder output, the first or the second transistor is conducting, whereby the selected cells are subjected to a voltage having a magnitude of .vertline.V3-V1.vertline. and the non-selected cells are subjected to a voltage having a magnitude of .vertline.V3-V2.vertline..

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Fontainebleau, France

Herve L Beranger