Vlsi Technology, Inc.

Herve G Duprez

David C Chapman

Pei H Lin

The present invention is directed to methods to assist designing integrated circuits by verifying that design constraints (e.g., minimum path width) are satisfied between two arbitrary nodes of a circuit layout. In an exemplary embodiment, a method for designing an integrated circuit layout by verifying that predetermined design constraints are satisfied for an arbitrary path defined by at least two nodes, comprises the steps of labeling all polygons of the integrated circuit layout with a name which corresponds to a layer of the integrated circuit layout in which each polygon is located, creating a file of polygons which includes polygons located along the arbitrary path, and determining whether polygons located along the arbitrary path satisfy predetermined design constraints specified for that path.

Method for verifying circuit layout design

A method for labelling polygons of a geometric layout which includes the steps of scanning a geometric layout during a first scan line pass to detect objects which form a polygon, processing the scan line at each occurrence of an event to detect the objects which contact the scan line, assigning temporary numbers and root designators to the objects which contact the scan line in accordance with a sorting criterion, updating the temporary numbers assigned to the objects to keep the temporary number associated with the earliest root designator of each separately detected polygon, and renaming each object which forms a part of the same polygon with a common label. The step of updating includes the steps of numbering each object in a polygon with a temporary number assigned to a root object of the polygon, and storing, in a sorted order, the root objects which lose their status as root objects during the step of updating.

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Campbell, CA, United States of America

Herve G Duprez