Nxp B.v.

Hervé Fleury

Jean-Marc Yannou

Tom Waayers

Fabrice Verjus

Johan Corneel Meirlevede

Ruediger Solbach

Jozef R Poels

Philippe L L Cauvet

David P Price

Hervé Vincent

Norbert Schomann

A method is provided for testing an integrated circuit comprising multiple cores, with at least two cores having different associated first and second clock signals of different frequencies. A test signal is provided using a clocked scan chain clocked at a test frequency (TCK). A transition is provided in a clock circuit reset signal (clockdiv_rst) which triggers the operation of a clock divider circuit () which derives the first and second clock signals (clk_xx, clk_yy, clk_zz) from an internal clock () of the integrated circuit. The first and second clock signals thus start at substantially the same time, and these are used during a test mode to perform a test of the integrated circuit. After test, the test result is output using the clocked scan chain clocked at the test frequency (TCK). Clocking hardware is also provided, and these provide at-speed testing which enables on the fly switching between a relatively slow tester driven clock for the shift modes and faster clocks generated by on-chip PLLs and divider circuits for the test mode.

IC testing methods and apparatus

A system in package () has a, preferably wireless, test controller () for testing each die () after it has been mounted onto the substrate of the system in package (), and a faulty die () is repaired before a next die () is mounted onto the substrate (). This way, the system in package () can be tested during the intermediate stages of its manufacturing, thus ensuring that all dies () function correctly before sealing the dies in the single package. Consequently, a method for manufacturing a system in package () is obtained that has an improved yield compared to known manufacturing methods.

Method of manufacturing a system in package

An electronic circuit contains groups of flip-flops (-), coupled to data terminals (-) of the circuit and to a functional circuit (). Each group (-) has a clock input for clocking the flip-flops of the group. Each group (-) can be switched between a shift configuration and a functional configuration, for serially shifting in test data from the data terminals and to function in parallel to supply signals to the functional circuit () and/or receive signals from the functional circuit () respectively. A test control circuit () can be switched between a functional mode, a test shift mode and a test normal mode. The test control circuit () is coupled to the groups of flip-flops (-) to switch the groups to the functional configuration in the functional mode and to the shift configuration in the test shift mode. A clock multiplexing circuit (-) has inputs coupled to the data terminals (-) and outputs coupled to clock inputs of the groups (-). The test control circuit () is coupled to control the clock multiplexing circuit (-) dependent on the mode assumed by the test control circuit (). The clock multiplexing circuit (-) is arranged to substitute clock signals from respective ones of the data terminals (-) temporarily at the clock inputs of respective ones of the groups (-) in the test normal mode.

Testable electronic circuit

The invention relates to an electronic circuit including a sub-module assembly () connected to the rest of the circuit, the sub-module assembly including a secret sub-module () for performing a function, scan chains; a built-in self test circuit including a pattern generator () to apply input signals to the scan chains, and a signature register () to check output signals from the scan chains. In order to keep the sub-module secret, the scan chains are not connected to the rest of the circuit.

Electronic circuit comprising a secret sub-module

Growing community of inventors

Caen, France

Hervé Fleury