Stmicroelectronics (rousset) Sas

Stmicroelectronics S.a.

Université De Provence (aix-marseille I)

Stmicroelectronics Gmbh

Universite De Provence Aix-marseilles

Université De Provence

Hervé Chalopin

Laurent Tabaries

François Tailliet

Gilles Bas

Philippe Courmontagne

Anne Collard-Bovy

Marc Battista

Hervé Barthelemy

A method to transmit data over a single-wire bus wherein a first communication channel is defined by pulses of different durations according to the state of the transmitted bit and depending on a reference duration, and a second communication channel is defined by the reference duration.

Single-wire bus communication protocol

A method for transmitting data over a single-wire bus wherein a first communication channel is defined by pulses of different durations according to the state of the transmitted bit and depending on a reference duration, and a second communication channel is defined by the reference duration.

Single wire bus communication protocol

A method of conversion by at least one interface circuit connected between a first bus including at least one data wire and one clock wire, and at least one second single-wire bus, of a transmission between a master circuit connected to the first bus and at least one slave circuit connected to the second bus, wherein a speculative read command is sent to the slave circuit before interpreting the state of a bit for controlling a reading or a writing, originating from the master circuit.

Conversion of a two-wire bus into a single-wire bus

A method for authenticating a transmission between a first and a second circuit transiting through at least one third circuit, wherein: data are transmitted from the first to the third circuit, and from the third to the second circuit; a first signature of the data is calculated by the first circuit; at least a second signature of the data is calculated by the third circuit; at least one first portion of the first signature is transmitted by the first circuit to the third one; and the second signature is transmitted by the third circuit to the second one, a portion of this signature being distorted in case of a failure of authentication of the first portion of the first signature by the third circuit.

Multiprotocol communication authentication

The pulse train of a signal is modulated by a DPIM modulation involving a discrete random time parameter. A first processing is performed on the signal to deliver a sampled signal. A second processing is performed on the sampled signal, comprising a correlation processing including at least one elementary correlation processing with a correlation mask corresponding to the shape of at least part of a sampled pulse, and delivering second information items. A third processing is performed for detecting the pulses following a first pulse by taking account of the position of the first pulse, on packets of second information items, which are separated by a duration related to the discrete random parameter.

Method and device for processing a pulse train of a modulated signal, in particular an ultra wideband signal modulated by a digital pulse interval modulation

An integrated circuit including a semiconductor layer; and a MOS transistor including first and second power terminals and a bulk insulated from the semiconductor layer, the first power terminal being intended to receive an oscillating signal, the transistor gate and the bulk being connected to the first power terminal.

Electronic circuit having a diode-connected MOS transistor with an improved efficiency

The waveform of the signal varies according to the distance at which the signal was emitted, and several correlation signals are defined and correspond respectively to at least part of several sampled waveforms of the signal respectively emitted at several distances of different values so that the sum of the maxima of intercorrelations performed respectively between the various correlation signals and the various sampled waveforms is substantially constant over an interval including all the values of the distances. The correlation processing includes several elementary correlation processings respectively performed with the correlation signals and each delivering initial correlation values, as well as a summation of the homologous initial correlation values respectively delivered by the elementary correlation processings so as to obtain the correlation values.

Method and device for correlating a signal, in particular an ultra wideband signal

An interface communicates between two communication buses which use at least two different protocols. The interface includes a volatile memory having at least two access ports and including two transcoding circuits, each transcoding circuit being specific to each of the protocols to be interfaced.

Communication interface

A programmable control interface is for circuits using complex commands. The programmable interface includes a memory for storing sampled commands and a sequencing circuit. The sequencing circuit is programmable. Thus, a processor downloads into the programmable interface a sequencing specific to the sequence of commands. Once the programmable interface has been programmed, the processor launches the start of the sequence and the programmable interface manages and controls in a standalone manner the inputs/outputs with the slave circuit. The management and control of the slave circuit is independent of any interrupt specific to the system. The programmable interface uses a software-type upgrade to interface with new slave circuits that may appear on the market.

Programmable control interface device

An electronic system comprises a defined number N of functional modules, including a defined number P of initiator modules and a defined number Q of target modules, where N, P and Q are integer numbers such that 2&#x2266;P&#x2266;N and 1&#x2266;Q&#x2266;N. In the event of a plurality of conflicting requests to access a common resource originating from a plurality of respective initiator modules, an arbitration unit grants an exclusive right of access to the resource to a defined one of these initiator modules. The arbitration unit is constructed either to apply a standard arbitration mechanism to these respective initiators, or to apply as a priority a specific arbitration mechanism only to the members of a subset of these initiator modules, for each of which it receives a linked privileged access signal.

System on a chip with an arbitration unit to grant right of access to a common resource in response to conflicting requests for access from initiator modules, and storage key incorporating the arbitration unit

An electronic system comprises a control unit for ordering the storage of an index value for indexed registers, in an additional index register linked to a defined initiator module, in response to a request to write the index value in an index register linked to the indexed registers, initiated by the initiator module. In response to any request to access an indexed register initiated by a defined initiator module, the control unit copies the index value from the additional index register linked to this initiator module to the index register linked to this indexed register, prior to execution of the access request. This enables management of access to indexed registers associated with an arbitration mechanism provided for managing conflicting access requests initiated by different functional modules in a system on a chip.

Management of indexed registers in a system on a chip

An electronic system comprises an initiator module and a target module addressable by the initiator module, and an interface and control module for interfacing between respective communication protocols of the initiator module and of the target module. The interface and control module is constructed to set a composite instruction detection signal in response to the detection of a composite instruction executed by the initiator module, which composite instruction detection signal is used for the interfacing. The interface and control module is constructed to detect a composite instruction executed by the initiator module when, at a determined clock cycle of the initiator module, a change of the elementary operation executed by the initiator module is detected with respect to the previous clock cycle of the initiator module, while, at the same time, a signal for selecting the target module which was active is kept active.

Interfacing of functional modules in an on-chip system

An electronic system comprises an initiator module and a target module addressable by the initiator module. The initiator module is activated by edges of an activation signal generated from a first clock signal having a frequency. A control module is activated by edges of a second clock signal having a frequency, which is at least twice as large as the frequency of the first clock signal. The control module is constructed so as, in response to an request for access to the target module, initiated by the initiator module on an active edge of the activation signal, to set a signal for blocking the activation signal before the next edge of the latter, and to reinitialize the blocking signal on the first active edge of the first clock signal which follows the indication by the target module that the processing of the request is terminated at the target module.

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Aubagne, France

Hervé Chalopin