Chang Gung University

Herng-Jer Lee

Chia-Chi Chu

Wu-Shiung Feng

Ming-Hong Lai

Chao-Kai Chang

Chia-Ming Ho

The adjoint network reduction technique has been shown to reduce 50% of the computational complexity of constructing the congruence transformation matrix. The method was suitable for analyzing the special multi-port driving-point impedance of RLC interconnect circuits. This technique is extended for the general circumstances of RLC interconnects. Comparative studies among the conventional methods and the proposed methods are also investigated. Experimental results will demonstrate the accuracy and the efficiency of the proposed method.

Generalizations of adjoint networks techniques for RLC interconnects model-order reductions

A model reduction method utilizing the rational Arnoldi method with adaptive orders (RAMAO) is applied to high-speed VLSI interconnect models. The method is based on an extension of the classical multi-point Pade approximation, using the rational Arnoldi iteration approach. Given a set of predetermined expansion points, an exact expression for the error between the output moment of the original system and that of the reduced-order system, related to each expansion point, is derived first. In each iteration of the proposed RAMAO algorithm, the expansion frequency corresponding to the maximum output moment error will be chosen. Hence, the corresponding reduced-order model yields the greatest improvement in output moments among all reduced-order models of the same order.

Multi-point model reductions of VLSI interconnects using the rational Arnoldi method with adaptive orders

An interconnect model-order reduction method reduces a nano-level semiconductor interconnect network as an original interconnect network by using iteration-based Arnoldi algorithms. The method is performed based on a projection method and has become a necessity for efficient interconnect modeling and simulations. To select an order of the reduced-order model that can efficiently reflect essential dynamics of the original interconnect network, a residual error between transfer functions of the original interconnect network and the reduced interconnect model may be considered as a reference in determining if the iteration process should end, with analytical expressions of the residual error being derived herein. Furthermore, the approximate transfer function of the reduced interconnect model may also be expressed as an addition of the original interconnect model and some additive perturbations. A perturbation matrix is only related with resultant vectors at a previous step of the Arnoldi algorithm. Therefore, the residual error information may be taken as a reference for the order selection scheme used in Krylov subspace model-order algorithm.

Interconnect model-order reduction method

A method and apparatus for designing low-order linear-phase IIR filters is disclosed. Given an FIR filter, the method utilizes a new Krylov subspace projection method, called the rational Arnoldi method with adaptive orders, to synthesize an approximated IIR filter with small orders. The method is efficient in terms of computational complexity. The synthesized IIR filter can truly reflect essential dynamical features of the original FIR filter and indeed satisfies the design specifications. In particular, the linear-phase property is stilled remained in the passband.

Efficient digital filter design tool for approximating an FIR filter with a low-order linear-phase IIR filter

A moment computation technique for general lumped R(L)C interconnect circuits with multiple resistor loops is proposed. Using the concept of tearing, a lumped R(L)C network can be partitioned into a spanning tree and several resistor links. The contributions of network moments from each free and the corresponding links can be determined independently. By combining the conventional moment computation algorithms and the reduced ordered binary decision diagram (ROBDD), the proposed method can compute system moments efficiently. Experimental results demonstrate that the proposed method can indeed obtain accurate moments and is more efficient than the conventional approach.

Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops

Computer time for modeling VLSI interconnection circuits is reduced by using symmetric properties of modified nodal analysis formulation. The modeling uses modified nodal analysis matrices then applies a Krylov subspace matrix to construct a congruence transformation matrix to generate the reduced order model of the VLSI.

Method and apparatus for model-order reduction and sensitivity analysis

A method and apparatus for rapidly selecting types of buffers which are inserted in the clock tree for high-speed VLSI design is disclosed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure minimizing the clock delay and satisfying the clock skew constrains. Given the clock tree netlist, the inserted buffers location information, the wire electrical parameters and a buffers timing library, the components delay (buffer delay and wire delay) of the clock tree can be calculated first. Then, for each I/O pin, the path delay, the clock delay and the clock skew can be obtained. Finally, using the method, a modified clock tree netlist satisfying the timing specifications can be constructed.

Method and apparatus for rapidly selecting types of buffers which are inserted into the clock tree for high-speed very-large-scale-integration

A method for reordering a scan chain meets given constraints and minimizes peak power dissipation. The given constraints include a maximum peak power dissipation, a maximum scan chain length and a maximum distance between two successive registers. The method includes embedding a developed tool into an existing VLSI design flow for low-power circuit designs. Furthermore, the characteristics quickly judge if the problem has corresponding feasible solutions and searching the optimal solution. Modified data from the given scan chain declaration data and the scan pattern data, which satisfy the constraints, can be obtained.

Method on scan chain reordering for lowering VLSI power consumption

A method for efficiently estimating crosstalk noise of high-speed VLSI interconnects models high-speed VLSI interconnects as lumped RLG coupled frees. An inductive crosstalk noise waveform can be accurately estimated in an efficient manner using a linear time moment computation technique in conjunction with a projection-based order reduction method. Recursive formulas of moment computations for coupled RC trees are derived taking into consideration of both self inductances and mutual inductances. Also, analytical formulas of voltage moments at each node will be derived explicitly. These formulas can be efficiently implemented for use in crosstalk estimations.

Method of estimating crosstalk noise in lumped RLC coupled interconnects

A method and verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits is provided. In this invention, nanometer VLSI interconnects are modeled as distributed RLC coupled trees. The efficiency and the accuracy of moment computation of distributed lines can be shown that outperform those of lumped ones. The inductive crosstalk noise waveform can be accurately estimated in an efficient manner using the linear time moment computation technique in conjunction with the projection-based order reduction method. Recursive formulas of moment computations for coupled RC trees are derived with considering both self inductances and mutual inductances. Also, analytical formulas of voltage moments at each node will be derived explicitly. These formulas can be efficiently implemented for crosstalk estimations.

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Tao-Yuan, Taiwan

Herng-Jer Lee