Infineon Technologies Ag

Siemens Aktiengesellschaft

International Business Machines Corporation

Samsung Electronics Co., Ltd.

Advanced Micro Devices Corporation

Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Hermann Wendt

Hans Reisinger

Volker Lehmann

Reinhard J Stengl

Martin Franosch

Gerrit Lange

Josef Willer

Herbert Sch&auml;fer

Erdem Kaltalioglu

Armin Tilke

Thomas Fischer

Alois Gutmann

Markus Naujok

Muhammed Shafi Pallachalil

Volker Weinrich

Gudrun Stranzl

Markus Menath

Frank Huebinger

Ulrike Gr&uuml;ning

Wolfgang Raberg

Manfred Engelhardt

Dietrich Bonart

Klemens Pruegl

Helmut Klose

Bernhard Weidgans

Philipp Riess

Thomas Peter Haneder

Gerhard Beitel

Wolfgang Hoenlein

Andreas Strasser

Herbert Schaefer

Tobias Schmidt

Harald Bachhofer

Igor Kasko

Wolfgang H&ouml;nlein

Stefan Ottow

Ulrike Gruning

Elke Fritsch

Franz Hofmann

Rainer Leuschner

Walter Hartner

Kaushik Arun Kumar

Wolfgang Krautschneider

Bernhard Goller

Siegfried Schwarzl

Nicolas Nagel

Rainer Bruchhaus

Frank S Hintermaier

Ravi Prakash Srivastava

Dietrich Widmann

Michael Roesner

Thomas Meister

Christine Dehm

Johnny Widodo

G&uuml;nther Schindler

Martin Zgaga

Michael Beck

Wuping Liu

Hanno Melzner

Klaus Goller

Larry Clevenger

Wan-jae Park

Werner Pamler

Anthony David Lisi

Stefan Miethaner

Teck Jung Tang

Alfred Kersch

Moosung Chae

Berthold Schuderer

Karl Mayer

Hans-Willi Meul

Andreas Spitzer

Jing Li

Lothar Doni

Robert Primig

Marcus Culmsee

Bee Kim Hong

Anja Reitmeier

Stefan Eckert

Monika Cornelia Voerckel

Anja Gissibl

Bernhard Boche

Stephan Schlamminger

Reinhard Stengel

Thomas Bohm

Han Wah Ng

Joseph Edward Linville

Bernd Noehammer

Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.

Methods for processing a semiconductor workpiece

A magnetoresistive device that can include a magnetoresistive stack and an etch-stop layer (ESL) disposed on the magnetoresistive stack. A method of manufacturing the magnetoresistive device can include: depositing the magnetoresistive stack, the ESL and a mask layer on a substrate; performing a first etching process to etch a portion of the mask layer to expose a portion of the ESL; and performing a second etching process to etch the exposed portion of the ESL. The second etching process can also etch a portion of the magnetoresistive stack. The first and second etching processes can be different. For example, the first etching process can be a reactive etching process and the second etching process can be a non-reactive etching process.

Magnetoresistive devices and methods for manufacturing magnetoresistive devices

A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.

Transformer comprising a rounded coil

A magnetoresistive device that can include a magnetoresistive stack and an etch-stop layer (ESL) disposed on the magnetoresistive stack. A method of manufacturing the magnetoresistive device can include: depositing the magnetoresistive stack, the ESL and a mask layer on a substrate; performing a first etching process to etch a portion of the mask layer to expose a portion of the ESL; and performing a second etching process to etch the exposed portion of the ESL and a portion of the magnetoresistive stack. The method can further include depositing a photoresist layer on the hard mask before the first etching process and removing the photoresist layer from the hard mask following the first etching process. The first and second etching processes can be different. For example, the first etching process can be a reactive etching process and the second etching process can be a non-reactive etching process.

A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.

Semiconductor devices and structures thereof

A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.

Method for processing a semiconductor workpiece with metallization

Method for fabricating a coil by way of a rounded trench

Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.

Devices formed with dual damascene process

A method includes structuring a semiconductor substrate to produce a number semiconductor chips. Each of the semiconductor chips includes a first main face and a number of side faces. An indentation is formed at a transition between the first main face and the side faces.

Method for fabricating a semiconductor chip and semiconductor chip

Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels.

Crack stop trenches

Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.

Methods of manufacturing semiconductor devices

Dual damascene process

Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.

Methods of patterning insulating layers using etching techniques that compensate for etch rate variations

Growing community of inventors

Poughkeepsie, NY, United States of America

Hermann Wendt