Texas Instruments Incorporated Deutschland, Gmbh

Texas Instruments Corporation

Hermann Seibold

Puneet Sareen

Joerg Kirchner

Markus Dietl

Gerd Rombach

Ivo Huber

Methods and apparatus for operating a DC-to-DC voltage converter that has a power stage that includes at least one switching transistor. The output voltage of the DC-to-DC voltage converter is monitored. If the output voltage drops below a lower output voltage threshold, a series of drive pulses is provided to the at least one switching transistor to commence switching of the at least one switching transistor. If the output voltage rises above an upper output voltage threshold, a random number of additional drive pulses is provided to the at least one switching transistor and then the provision of drive pulses to the at least one switching transistor is ceased.

Implementation of spread spectrum in PFM mode for DC-DC converters

An electronic device is provided that includes a power-on-reset (POR) circuit. The POR circuit includes a trigger stage configured to change an output if a first power supply voltage level exceeds a threshold voltage level and a first inverter and a second inverter being cross-coupled. An output of the second inverter is the POR output of the power-up reset circuit. The output is coupled to the trigger stage for switching the trigger stage off in response to a change of a signal at the output of the second inverter. The first inverter is dimensioned to follow with a voltage level at an output an initially rising slope of the first power supply voltage level and the second inverter is dimensioned to keep a voltage level at an output at a second power supply voltage level during the initially rising slope of the first power supply voltage level.

Electronic device for power-on-reset

In applications that use fractional-N phase locked loops (PLLs), the use of spread spectrum clocking (SSC) to reduced electromagnetic interference (EMI) would be desirable, but conflicts can occur. Here, a circuit is provided that includes both fractional logic circuitry and spread spectrum logic circuitry. This logic circuitry operates in combination with a phase selector to generally ensure that the likelihood of conflicts (which can occur in conventional circuit) are reduced.

Spread spectrum clocking in fractional-N PLL

A clock generator including a PLL circuit serves to generate an output frequency cycled in a predefined range and containing a desired clock frequency. The PLL circuit contains a voltage-controlled oscillator ( ), the oscillating frequency of which is adjustable by means of an analog control voltage to the desired clock frequency in a fixed relationship to a reference frequency applied to the PLL circuit. The clock generator contains a second voltage-controlled oscillator ( ), the oscillating frequency of which can be cycled in the predefined range. The second oscillator ( ) is configured so that its oscillating frequency can be varied by means of a digital incrementally variable control signal in the predefined range. By varying the output frequency of the clock generator a spreading of its output frequency spectrum is attainable, resulting in a reduction in high-frequency interference by the signal generated by the clock.

Clock generator circuit with a PLL having an output frequency cycled in a range to reduce unwanted radiation

A phase-locked loop (PLL) has a phase detector coupled to an output of the PLL and to a reference signal and a low pass filter including a first and a second charge pump coupled to an output of the phase detector. A capacitor is coupled to an output of the first charge pump, a first bias circuit coupled to the capacitor, the first bias circuit having a differential output. A voltage controlled ring oscillator has a plurality of differential inventer stages, each having a first input coupled to a first output of the first bias circuit and a second input coupled to a second output of the first bias circuit. A second bias circuit is coupled between the capacitor and the first bias circuit, an output of the second bias circuit being coupled to an input of the first bias circuit and to an output of the second charge pump. The PLL circuit exhibits a stable damping factor with respect to frequency.

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Haag, Germany

Hermann Seibold