Infineon Technologies Ag

Qimonda Ag

Other

Infineon Technologies LLC

Qimonda

Hermann Ruckerbauer

Peter Gregorius

Johannes Stecker

Georg Braun

Michael Bruennert

Maksim Kuzmenka

Dominique Savignac

Paul Wallner

Dirk Scheideler

Christoph Bilger

Maurizio Skerlj

Roland Barth

Wolfgang Walthes

Christian Sichert

Andreas Jakobs

George William Alexander

Simon Muff

Ralf Schledz

Andre Sch&auml;fer

Thomas Hein

Wolfgang Anton Spirkl

Oliver Kiehl

Thilo Schaffroth

Christian Robert Mueller

Ullrich Menczigar

Martin Maier

Ralf Schedel

Christian Weiss

Andreas Gärtner

Andreas Gaertner

Helmut Schneider

Florian Schamberger

Roland Irsigler

Richard Johannes Luyken

Daniel Kehrer

Martin Streibl

Justus Kuhn

J&uuml;rgen Lindolf

Srdjan Djordjevic

Siva RaghuRam

Sven Kalms

Abdallah Bacha

Steve Wood

Thomas Borst

Holger Schroeter

Amir Motamedi

Frank Thiele

Sitt Tontisirin

Sitt Tontosirin

Carsten Niepelt

Christian Weiβ

Peter Oeschay

Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.

Multi-port DRAM architecture for accessing different memory partitions

A chip includes a memory array and a refresh counter. The refresh counter is configured to receive refresh trigger signals. The refresh counter is configured or configurable to initiate a refresh of the memory array only once per i of the received refresh trigger signals where i is a number greater than 1.

Chip, multi-chip system in a method for performing a refresh of a memory array

A system and method utilize a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated with a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, a plurality of memory devices may be arranged in a memory package in a stacked die memory configuration.

Method and system including plural memory controllers and a memory access control bus for accessing a memory device

An electronic device provides a stack of semiconductor chips. A redistribution layer of a first semiconductor chip is arranged at the bottom of the stack. The redistribution layer of the first semiconductor chip comprises external pads.

Electronic device having a chip stack

A system including a central processing unit, a first memory channel being configured to couple the central processing unit to a first semiconductor memory unit, wherein the first memory channel is configured to be clocked with a first clock frequency, and a second memory channel being configured to couple the central processing unit to a second semiconductor memory unit, wherein the second memory channel is configured or configurable to be clocked with a second clock frequency smaller than the first clock frequency.

Memory system with extended memory density capability

A memory circuit includes multiple memory chips configured to store data and disposed in at least one stack. The memory circuit includes multiple ports configured to receive and transmit control signals and data to and from the memory chips and to supply energy to the memory circuit. The memory circuit includes a housing accommodating the multiple memory chips and the multiple ports.

Memory circuit having memory chips parallel connected to ports and corresponding production method

Distributed command and address bus architecture for memory modules and circuit boards is described. In one embodiment, a memory module includes a plurality of connector pins disposed on an edge of a circuit board, the plurality of connector pins comprising first pins coupled to a plurality of data bus lines, second pins coupled to a plurality of command and address bus lines, wherein the second pins are disposed in a first and a second region, wherein a portion of the first pins is disposed between the first and the second regions.

Distributed command and address bus architecture for a memory module having portions of bus lines separately disposed

The invention provides a method and an apparatus for determining a skew of each data bit of an encoded data word received by a receiver via an interface from a transmitter comprising the steps of performing an error check and correction of the received and sampled encoded data word to calculate an error corrected encoded data word corresponding to the encoded data word transmitted by the transmitter, and correlating a sequence of error corrected encoded data words with the sampled encoded data words to determine a skew of each data bit of said received encoded data words.

Method and apparatus for determining a skew

The multi-die memory comprises a first die and a second die. The first die comprises a first group of memory banks, and the second die comprises a second group of memory banks. The first group of memory banks and the second group of memory banks are coupled to a common memory interface. The common memory interface couples the multi-die memory with an internal connection.

Multi-die memory, apparatus and multi-die memory stack

A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus.

Bus termination system and method

The invention provides a memory circuit comprising a plurality of storage cells for storing data and redundant spare storage cells for replacing defective storage cells, and a memory access logic for accessing said storage cells connected to a replacement setting register which is writeable during operation of said memory circuit to store replacement settings.

Memory circuit

A method for operating a memory apparatus which comprises at least two memory devices, each memory device containing at least one bank, comprising: activation of at least one word line in at least one bank on the basis of a row activation command; storage of bank information, the bank information indicating which banks per memory device contain a word line activated by the row activation command; reading/writing of memory contents from/to banks with activated word lines on the basis of the bank information.

Method of operating a memory apparatus, memory device and memory apparatus

A memory apparatus includes at least two memory devices, each memory device including at least one memory bank. A method of operating the memory apparatus includes receiving a row activation command generated by a memory controller, wherein the row activation command includes a bank address. The method also includes activating a word line in a bank of one of the memory devices based on the row activation command, wherein the bank address is used to select the memory device.

Embodiments of the invention relate to an integrated circuit comprising at least one functional unit configured to operate at a first clock frequency. The integrated circuit also comprises at least one first interconnect originating from a contact pad and leading to at least one frequency divider configured to receive a clock signal having a second frequency and generate one or more clock signals to operate the functional unit at the first frequency. The integrated circuit further comprises at least one second interconnect coupling an output of the frequency divider and an input of the functional unit, wherein a total length of the second wired interconnect is less than a total length of the first wired interconnects.

Methods and articles of manufacture for operating electronic devices on a plurality of clock signals

An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.

Integrated circuit with wireless connection

Growing community of inventors

Moos, Germany

Hermann Ruckerbauer