Intel Corporation

Hermann Gartler

Robert S Chappell

David W Burns

Michael D Tucknott

John Faistl

Per H Hammarlund

Rajesh S Parthasarathy

Michael Neve De Mevergnies

William Penner

Michael S Bair

Glenn J Hinton

Martin Guy Dixon

Stephan Jourdan

David W Grawrock

David A Koufaty

Ronak Singhal

Tsvika Kurts

Kevin Safford

Erik J Johnson

Bruce Querbach

Larisa Novakovsky

Yoni Aizik

Frank Binns

Tieyu Zheng

Camron B Rust

Hisham Shafi

Keshavan K Tiruvallur

Mark B Trobough

Aaron R Kunze

Chinna B Prudvi

Sebastien Hily

Vui Yong Liew

Ashok N Kabadi

Keith A Drescher

Samie B Samaan

Jay Joseph Nejedlo

Mukesh Kataria

Lyle E Cool

James J Grealish

Russell J Wunderlich

Abhijit Davare

Brian Meyer

Michael J St Clair

Aravindh Baktha

Ki W Yoon

Priyadarsan Patra

Rahima K Mohammed

Ridvan A Sahan

Brad Bickford

Wee Hoo Cheah

John L Baudrexl

Yuen Tat Lee

Arun R Ramadorai

Christopher J Shannon

Kapila B Udawatta

Loren James McConnell

Russ Hampsten

Aleph Fackenthall

Joseph Bursey

Kip C Killpack

Kyle Markley

Christian E Iovin

Jiun Long Foo

Selvakumar Raja Gopal

Neil Dobler

Nagib Z Hakim

Timothy S Storey

Yi Amy Xia

Edwin E Parks

Padmakumar Gopal

Sanjay S Salem

David C Florey

Rajesh S Parathasarthy

Travis K Goff

Evan J Halprin

Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.

Supporting hang detection and data recovery in microprocessor systems

A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

Method and apparatus for bus lock assistance

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Test, validation, and debug architecture

A chassis platform, such as processor or a system-on-chip (SoC), includes logic to implement a debug chassis security system including a policy generator to control access from a test access port. The policy generator may distribute a debug policy to at least one logic block that locally enforces the debug policy. The debug policy may include a delayed authentication policy in which debug assets are distributed and the chassis platform is initially locked to prevent debug access via the test access port. An authenticated debug user may unlock the chassis platform at a later time to enable debugging operations. The debug policy may also include a live execution policy and an immediate debug policy.

Delayed authentication debug policy

Apparatuses and methods for steering SMM code region accesses are disclosed. In one embodiment, an apparatus includes a status indicator, a base storage location, and an abort storage location. The status indicator is to indicate whether the apparatus is operating in SMM. The base storage location is to store a base address and the abort storage location is to store an abort address. The base address is to specify a first memory address region at which SMM code is to be accessed. The abort address is to specify a second memory address region to which accesses to the first memory address region are to be steered if the apparatus is not operating in SMM.

Steering system management code region accesses

In some embodiments, the invention involves a novel combination of techniques for prefetching data and passing messages between and among cores in a multi-processor/multi-core platform. In an embodiment, a receiving core has a message queue and a message prefetcher. Incoming messages are simultaneously written to the message queue and the message prefetcher. The prefetcher speculatively fetches data referenced in the received message so that the data is available when the message is executed in the execution pipeline, or shortly thereafter. Other embodiments are described and claimed.

Method and apparatus for speculative prefetching in a multi-processor/multi-core message-passing machine

In one embodiment, the present invention includes a method for receiving a cache access request for data present in a lower-level cache line of a lower-level cache, and sending recency information regarding the lower-level cache line to a higher-level cache. The higher-level cache may be inclusive with the lower-level cache and may update age data associated with the cache line, thus reducing the likelihood of eviction of the cache line. Other embodiments are described and claimed.

Synchronizing recency information in an inclusive cache hierarchy

Embodiments of the present invention relate to cache coherency. In an embodiment of the invention, a cache includes one or more cache lines. A store pipeline may retrieve a tag associated with one of the cache lines. The data associated with the cache line may not retrieved and the cache line may be updated if, based on the tag, the cache line is determined to be in a modified or exclusive state.

Decoupling request for ownership tag reads from data read operations

Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient cache memory management. The method includes writing an entry to a store buffer at execute time; determining if the entry's address is in a first-level cache associated with the store buffer before retirement; and setting a status bit associated with the entry in said store buffer, if the address is in the cache in either exclusive or modified state. The method further includes immediately writing the entry to the first-level cache at or after retirement when the status bit is set; and de-allocating the entry from said store buffer at retirement. The method further may comprise resetting the status bit if the cacheline is allocated over or is evicted from the cache before the store buffer entry attempts to write to the cache.

Apparatus and method for store address for store address prefetch and line locking

A riser card for use in a chassis includes a body having a first end and a second end. The length of the body is adequate to simultaneously allow the first end and the second end to be proximately situated at a back and a front wall of the chassis respectively. The riser card also includes a female edge connector disposed on the body that receives a male edge connector of a motherboard.

Extended riser for implementing a cableless front panel input/output

A device and method to eliminate contention for an accelerated graphics port (AGP). A video system includes an accelerated graphics port, a first location adapted to receive and couple an AGP controller to the accelerated graphics port, a second location adapted to receive and couple an AGP graphics accelerator chip to the accelerated graphics port, and at least one connector coupled to the accelerated graphics port that is adapted to receive an AGP graphics accelerator add-in card. Further, a device is coupled to the accelerated graphics port that selectively disables an AGP graphics accelerator chip coupled to the second location or an AGP graphics accelerator add-in card coupled to the connector.

Method and apparatus for eliminating contention on an accelerated

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Portland, OR, United States of America

Hermann Gartler