U.S. Philips Corporation

Other

Koninklijke Philips Corporation N.v.

Herman Schutte

Johan Hendrik Huijsing

Gerrit Van Der Horn

Frank R Riedijk

Martinus Bredius

Roeland F Tuk

Adrianus P Moelands

An electronic apparatus uses a bus conductor driven by wired logic to arbitrate between stations. When arbitration is decided, the apparatus switches to a higher speed mode by supplying additional current to the bus conductor, so that the winning station pulls the potential on the bus conductor against a greater current and the potential rises faster when the station stops pulling the potential.

Electronic apparatus

An electronic apparatus contains a bus conductor, a load circuit connected to the bus conductor for pulling a potential of the bus conductor towards a quiescent level and stations interconnected by the bus conductor. At least one of the stations contains a wired logic drive circuit and an arbitration circuit connected to the wired logic drive circuit for executing an arbitration wherein the wired logic drive circuits of different ones of the stations may each pull the potential against the load circuit. The electronic apparatus comprises a detector for producing a detection signal when the at least one station wins the arbitration. In response to the detection signal the load circuit is switched to an increased current supply capability state. In the increased current supply capability state the load circuit supplies a greater current to the bus conductor than during arbitration at least at times when the potential starts changing towards the quiescent level.

Electronic apparatus having a high-speed communication bus system such

A communication bus is split into two sections. When a station connected to one section indicates that it wishes to exchange a message at higher than normal speed via one section, a bridge station isolates the two sections, interrupting transfer of the content part of the message to the other section, and substitutes a dummy content part in the message on the other section.

Electronic network allowing multi-speed communication

Information is supplied to a bus in a wired logic function, the potential on the bus either being pulled down to ground level or remaining at supply level. The data line in a bus is split into two parts which are interconnected via the main current channel a transistor. Different supply voltages are used on the two parts. The control electrode of the transistor is connected to the lowest of the supply voltages. The transistor becomes conductive when either of the parts is pulled down. The transistor is non-conductive when none of the parts is pulled down.

Circuit comprising a data communication bus

A two-line multi-station bus system has a clock wire and a data wire and supports selective slave station addressing by a prevalent master station for thereupon eliciting a bitwise clocked data transfer between the clocking master station and an addressed and clocked slave station. Moreover, the system supports analog signal transfer in that the prevalent master station has a holding member for while eliciting the analog signal from the actual addressed slave station holding said clocking through carrying the clock wire at a predetermined binary value. The analog signal is received until changeover of the clock wire to a binary value other than the predetermined binary value a particular version the analog signal is pulse width modulated in combination with associate delimiting signals on the clock wire sent by the transmitter station that is not necessarily the master station.

Two-line mixed analog/digital bus system and a master station and a

Two-wire bus system comprises a clock wire and a data wire for interconnecting a number of stations and allowing both long-format and short-format slave addresses. A communication bus system has a single clock wire and a single data wire. Each wire has wired logic that upon presentation of any prevalence logic signal value imparts to that wire the prevalence logic value regardless of any non-prevalence value second presented thereto. The system has clock synchronization by a master station of any information transmission. The system arbitrates among coexistent prospective masters to select a single actual master. The protocol has a start condition by presenting said first value to the data wire with the clock line at the second value, and generates any subsequent data wire transition exclusively under existence of the prevalence value on the clock wire. The subsequent stop condition is represented by a transition to the second value on the data wire with the clock wire at the second value. The message format has an initial byte accommodating either a short slave address, or alternatively both a control signal indicating a long-format slave address inclusive of a high significance address part, to be followed in the next byte by a low significance part of the address. For enhancing the bit rate, the system has a switched pull up device, whereas furthermore each station has a slope controlled output stage.

Two-wire bus system comprising a clock wire and a data wire for

A computer system comprises a number of stations which are interconnected by means of a clock bus wire (20) and a data bus wire (22) which both form a wired logic function of the signals generated thereon by the stations (32, 34). During the clock pulses, the signal on the data bus wire is stationary; it may change between the clock pulses. Start and stop conditions are formed by a signal combination between clock bus wire and data bus wire (60 and 62, respectively) which is not permissible in a data stream. If there is more than one master station so that a composite clock signal occurs on the clock bus wire, the clocks of the relevant master stations are each time resynchronized to the actual transitions in the composite clock signal.

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Eindhoven, Netherlands

Herman Schutte