International Business Machines Corporation

Herman Lee Blackmon

Joseph Allen Kirscht

James Anthony Marcella

Kent Harold Haselhorst

Robert Allen Drehmel

David Alan Shedivy

Elizabeth A McGlone

Brian Thomas Vanderpool

David John Krolak

Ryan Scott Haraden

Lyle Edwin Grosbach

Peder James Paulson

Duane Arlyn Averill

John Michael Borkenhagen

William Paul Hovis

Philip Rogers Hillier, Iii

Ronald Ernest Freking

Jeb A Shookman

Elizabeth Mcglone

A periodic command spacing mechanism is provided for spacing periodic commands (e.g., refresh commands, ZQ calibration, etc.) to a volatile memory (e.g., SDRAM, DRAM, EDRAM, etc.) for increased performance and decreased collision. In one embodiment, periodic command requests are monitored and if a collision is detected between two or more of the requests, the colliding requests are spaced with respect to one another by a timer offset applied on a chip select basis. The periodic command spacing mechanism may be used in conjunction with command arbitration to make sure the periodic commands are executed without significantly impacting performance (e.g., Reads and Writes are allowed to flow). Preferably, the periodic command requests are initialized by generating an initial sequence of individual requests, each successive request in the initial sequence being generated spaced apart with respect to the previous request by a timer offset applied on a chip select basis.

Spacing periodic commands to a volatile memory for increased performance and decreased collision

A compressed replay buffer in a first electronic unit of an electronic system holds commands in a table. As commands are transmitted from the first electronic unit to a second electronic unit, the command, along with associated data, command type, and the like are stored in a row in the table. No rows in the table contain 'dead cycles' to indicate that no command was sent on a particular cycle on a bus over which the commands were transmitted. The second electronic unit may request that the first electronic unit replay some number of commands. In response, the first electronic unit uses commands in the compressed replay buffer, along with required timings stored on the first electronic unit, to replay the number of commands requested.

Compressed replay buffer

In a method of initializing a computer memory that receives data from a plurality of redrive buffers, a predetermined data pattern of a selected set of data patterns is stored in selected redrive buffers of the plurality of redrive buffers. Each of the selected set of data patterns includes a first initialization data pattern and an error correcting code pattern that is a product of a logical function that operates on the first initialization data pattern and an address in the computer memory. The selected set of data patterns includes each possible value of error correcting code pattern. A redrive buffer of the plurality of redrive buffers that has stored therein an error correcting code pattern that corresponds to the selected address is selected when sending a first initialization data pattern to a selected address. The selected redrive buffer is instructed to write to the selected address the first initialization data pattern and the error correcting code pattern that corresponds to the selected address.

Memory controller for reducing time to initialize main memory

Read commands on a mirrored memory computer system are scheduled by utilizing information about pending memory access requests. A conflict queue is configured to track a read/write queue associated with each of a plurality of memory ports on the mirrored memory system. The conflict queue determines a predicted latency on each memory port based on the contents of each of the read/write queues. A compare logic unit is coupled to the conflict queue, wherein the compare logic unit compares a predicted latency of a primary memory and a mirrored memory and schedules read commands to the memory port with the lowest predicted latency.

Memory controller for improved read port selection in a memory mirrored system

A method, apparatus, system, and signal-bearing medium that, in an embodiment, select a command to send to memory. In an embodiment, the oldest command in a write queue that does not collide with a conflict queue is sent to memory and added to the conflict queue if some or all of the following are true: all of the commands in the read queue collide with the conflict queue, any read command incoming from the processor does not collide with the write queue, the number of commands in the write queue is greater than a first threshold, and all commands in the conflict queue have been present for less than a second threshold. In an embodiment, a command does not collide with a queue if the command does not access the same cache line in memory as the commands in the queue. In this way, in an embodiment, write commands are sent to the memory at a time that reduces the impact on the performance of read commands.

Selecting a command to send to memory

In a method of managing a cache directory in a memory system, an original system address is presented to the cache directory when corresponding associativity data is allocated to an associativity class in the cache directory. The original system address is normalized by removing address space corresponding to a memory hole, thereby generating a normalized address. The normalized address is stored in the cache directory. The normalized address is de-normalized, thereby generating a de-normalized address, when the associativity data is cast out of the cache directory to make room for new associativity data. The de-normalized address is sent to the memory system for coherency management.

Method for increasing cache directory associativity classes in a system with a register space memory

In a method of generating a cache directory to include a plurality of associativity classes, each associativity class includes an address tag including a plurality of address bits. Each address tag is configured to store a unique address to a specific location in an memory space. An amount of memory that is in an actually configured portion of the memory space is determined. A minimum number of bits necessary to address each memory location in the actually configured portion of the memory space is determined. Each address tag is configured in each associativity class to include the minimum number of bits necessary to address each memory location in the actually configured portion of the memory space. The cache directory is configured to include a maximum number of associativity classes per line in the cache directory.

Method for increasing cache directory associativity classes via efficient tag bit reclaimation

A method, system, and computer program product for tuning a set of chipset parameters to achieve optimal chipset performance under varying workload characteristics. A set of workload characteristics of a current workload type is determined. An instruction stream is generated using weighted parameters derived from the set of workload characteristics of the current workload type. A set of chipset parameters is generated and integrated within the instruction stream. The instruction stream is loaded to one or more processors and executed to collect and analyze performance data relating to the chipset's performance. The analysis includes comparing the set of performance data of a plurality of different instruction streams having the same set of workload characteristics. Each executed instruction stream is executed with at least one different combination of chipset parameters. A determination is made regarding which combination of chipset parameters provides the best performance data for the current workload.

Method for tuning chipset parameters to achieve optimal performance under varying workload types

Methods and systems for re-ordering commands to access memory are disclosed. Embodiments may receive a first command to access a memory bank of the memory and determine a penalty associated with the first command based upon a conflict with an access to the memory bank. The penalty, in many embodiments, may be calculated so the penalty expires when the memory bank and a data bus associated with the memory bank are available to process the first command. Then, the first command is queued and dispatched to an available sequencer after the penalty expires. After the first command is serviced, unexpired penalties of subsequent commands may be updated to reflect a conflict with the first command. Further embodiments select a command to dispatch from the commands with expired penalties, based upon priorities associated with the commands such as the order in which the commands were received and the command types.

Methods and systems for re-ordering commands to access memory

A method and apparatus is provided which dynamically alters SDRAM memory interface timings to provide minimum read access latencies for different types of memory accesses in a memory subsystem of a computer system. The dynamic alteration of the SDRAM memory interface timings is based on workload and is determined with information from the memory controller read queue.

Dynamic optimization of latency and bandwidth on DRAM interfaces

An improved computer memory subsystem determines the most efficient memory command to execute. The physical location and any address dependency of each incoming memory command to a memory controller is ascertained and that information accompanies the command for categorization into types of command. For each type of memory command, there exists a command FIFO and associated logic in which a programmable number of the memory commands are selected for comparison with each other, with the memory command currently executing, and with the memory command previously chosen for execution. The memory command having the least memory cycle performance penalty is selected for execution unless that memory command has an address dependency. If more than one memory command of that type has the least memory cycle performance penalty, then the oldest is selected for execution. Memory commands of that type are selected for execution each subsequent cycle until a valid memory command of that type is no longer available, or until a predetermined number has been executed, or until a memory command of another type has higher priority. If an address dependency exists between memory commands of different types, then memory commands of the same type of the oldest memory command is executed to avoid deadlock.

Reordering and flushing commands in a computer memory subsystem

A method and system for arbitrating data transfers between devices connected via electronically isolated buses at a switch. In accordance with the method and system of the present invention, multiple arbitration controllers are interposed between devices and a switch to which the devices are connected, wherein each of the multiple arbitration controllers are effective to select a data transfer operation and detect collisions between said selected data transfer operations. The switch is enabled for any selected data transfer operations between which collisions are not detected. The switch is also enabled for only one of the selected data transfer operations between which collisions are detected. Any selected data transfer operations for which the switch is not enabled are deferred. The deferred data transfer operations are prioritized within the multiple arbitration controllers, such that for a subsequent selection of the deferred data transfer operations, the switch is enabled for the deferred data transfer operations.

Method and system for multilevel arbitration in a non-blocking crossbar switch

A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.

Shared bus non-sequential data ordering method and apparatus

A method and apparatus for routing data between bus devices, where each bus device is connected to a centralized switch via a point-to-point bus connection. The plurality of point-to-point bus connections collectively form a system bus. After a command is issued on the system bus, each bus device responds to the issued command by transmitting an address status response to a response combining logic module. The response combining logic module identifies which of the bus devices responded with a positive acknowledgment to the issued command, then forwards a device identifier of the bus device responding with the positive acknowledgment to the switch. The switch uses the device identifier returned via the response combining logic to route the data transfer associated with the issued command.

Data routing using status-response signals

An apparatus, program product and method initialize a redundant memory device by delaying the switchover of non-initialization fetch operations from a failed memory device to the redundant memory device until after initialization of the redundant memory device is complete. Consequently, during initialization, the non-initialization fetch operations are directed to the failed memory device, while non-initialization store operations are directed to the redundant device.

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Moline, IL, United States of America

Herman Lee Blackmon