Carnegie Mellon University

Herman Henry Schmit

Jeffrey Wayne Kidd

Christopher Maverick Petersen

Brian Christopher Van Essen

Ram K Krishnamurthy

L Richard Carley

Larry Pileggi

Akshay Aggarwal

Benjamin Levine

The present invention relates to a secure method of distributing configuration data for a programmable logic device (PLD). The configuration data is encrypted to generate encrypted configuration data. A decryption key is encrypted using a silicon key. The encrypted configuration data and the encrypted decryption key are transferred to a PLD. Within the PLD, the encrypted decryption key is decrypted using the silicon key. Then, also within the PLD, the encrypted configuration data is decrypted using the decryption key to recover the configuration data. The PLD is then configured using the configuration data. The silicon key may be communicated to the PLD by tying predetermined input pins to an active high voltage level or signal ground, to form a binary code.

Method of securing programmable logic configuration data

A method of associating virtual stripes to physical stripes in a pipelined or ring structure comprises associating a first set of virtual stripes with at least two physical stripes and associating a second set of virtual stripes, disjoint from the first set, with at least two additional physical stripes. The present invention is also directed to a method of configuring a plurality of processing elements based on a less than global, but not purely local, association. The configuration method of the present invention may be implemented in a device arranged in stripes of processing elements. The method comprises configuring either of at least two physical stripes with a virtual stripe from a first set of virtual stripes and configuring either of at least two additional physical stripes with a virtual stripe from a second set of virtual stripes, said first and second virtual sets being disjoint. The present invention is also directed to a reconfigurable device comprising a controller, a memory device responsive to the controller, a plurality of processing elements arranged in stripes, a plurality of intra-stripe interconnections for connecting processing elements within a stripe, a plurality of local inter-stripe connections for connecting the output of one stripe to the input of one and only one other stripe, a plurality of global inter-stripe connections for connecting at least one but less than all of the physical stripes to the memory, and an input bus and an output bus, each connected to at least one physical stripe.

Programmable pipeline fabric utilizing partially global configuration buses

A method and apparatus for storing and using 'register use' information to determine when a register is being used for the last time so that power savings may be achieved is disclosed. The register use information may take the form of 'last read' information for a particular register. The last read information may be used to force the value of the register, after being read, to zero or to clock only that register while masking off the other registers. Several methods and hardware variations are disclosed for using the register use information to achieve power savings.

Programmable pipeline fabric having mechanism to terminate signal propagation

A method is comprised of translating a bit stream defining the state of switches of an FPGA into a set of via geometries, or generating the set of via geometries directly from a physical design system. The via geometries are used to produce at least one via mask. The via mask is then used in a manufacturing process to customize an array of fixed and/or programmable logic blocks.

Programmable gate array based on configurable metal interconnect vias

A multiple power supply circuit architecture, such as a circuit power system including a first voltage rail, a first reference rail, a second voltage rail, a second reference rail, and a first selective connector between the first and second voltage rails.

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Pittsburgh, PA, United States of America

Herman Henry Schmit