Tabula, Inc.

Altera Corporation

Other

Intel Corporation

Easic Corporation

Google Inc.

Tbula, Inc.

Herman Henry Schmit

Steven L Teig

Jason Rupert Redgrave

Brad Hutchings

Michael Butts

Randy Renfu Huang

Andrew Edward Caldwell

Dana How

Michael David Hutton

Teju Khubchandani

David Lewis

Sean R Atsatt

Andre Rohe

Daniel J Pugh

Carl Ebeling

David Wolk Mendel

Andy Louie Lee

Jonathan C Park

Jiefan Zhang

Vikas Chandra

Mahesh A Iyer

Ramanand Venkata

Keith Duwel

Scott J Weber

Michial Allen Gunter

Sergey Vladimirovich Gribok

Huy X Ngo

Ting Lu

Adam E Levinthal

Jeffrey Christopher Chromczak

Bee Yee Ng

Thiam Khean Hah

Saurabh Adya

Tom Kronmiller

Reiner Alwyn Pope

Vadim Gutnik

Haiyun Yang

Soon Chieh Lim

Ronnie V Vasishta

Gaik Ming Chan

Vamsi Nalluri

Yit Ping Kok

Shu Ern Perng Mark

Teju Khubehandani

David Michael Lewis

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for sharding dataflow graphs for a device having multiple synchronous tiles. One of the methods includes receiving a representation of a dataflow graph comprising a plurality of nodes that each represent respective matrix operations to be performed by a device having a plurality synchronous tiles. Candidate allocations of respective portions of the dataflow graph to each tile of the plurality of synchronous tiles are evaluated according to one or more resource constraints of the device. One of the candidate allocations is selected based on evaluating each candidate allocation.

Sharding for synchronous processors

A programmable integrated circuit includes configuration circuitry configured to receive configurations of a user design for the programmable integrated circuit. Each of the configurations implements the user design using at least some unique circuitry in the programmable integrated circuit relative to the other ones of the configurations. The configuration circuitry is further configured to implement the user design in a first one of the configurations. The configuration circuitry is further configured to move the user design from the first one of the configurations to a second one of the configurations to cause effects of aging processes in circuits in the programmable integrated circuit that are not aged by the first one of the configurations.

Techniques for reducing uneven aging in integrated circuits

The present disclosure provides systems and methods for improving operation of integrated circuit device including a logic region, which includes a plurality of logic gates that operate based at least in part on a clock signal to facilitate providing a target function, and a clock tree, which includes a clock switch block that receives a source clock signal from a clock source and a branch communicatively coupled between the clock switch block and the logic region, in which the branch operates to provide the clock signal to the logic region based at least in part on the source clock signal and one or more tunable delay buffers, disposed at junctures of the clock network, that operate to apply a delay to the clock signal based at least in part on a clock skew expected to be introduced by the branch.

Distributed programmable delay lines in a clock tree

An integrated circuit includes first circuits that are configured to implement a user design for the integrated circuit, second circuits that are unused by the user design, and configuration circuitry that couples the second circuits together through a network of conductors. Transistors in the second circuits turn on and off in response to a varying signal that propagates through the second circuits and through the network of conductors while the first circuits implement the user design.

An integrated circuit may include multiple programmable logic regions and a first plurality of routers. Each of the first plurality of routers is coupled to a respective region of a first portion of the programmable logic regions, and each of the first portion of the plurality of regions transmits configuration data to a first set of adjacent regions of the first portion of regions. The integrated circuit may also include a second plurality of routers, and each of the second plurality of routers is coupled to a respective region of a second portion of the regions. Each of the second portion of the regions transmits the configuration data to a second set of adjacent regions of the first portion of regions. The integrated circuit may also include a voltage regulator that distributes a voltage to each of the regions.

Systems and methods for routing data across regions of an integrated circuit

Systems and methods are included for efficiently implementing learned parameter systems (LPSs) on a programmable integrated circuit (PIC) via a computing engine. The computing engine receives an input set of learned parameters corresponding to use instances of an LPS. The computing engine reduces at least some redundancies and/or unnecessary operations using instance specific parameter values of the LPS, to generate a less redundant set of learned parameters and a corresponding less redundant LPS. The computing engine generates a netlist based on these, which may share computing resources of the PIC across multiple computations in accordance with the less redundant set of learned parameters and the corresponding less redundant LPS. The computing engine then programs the PIC with the netlist. That is, the netlist replaces use instances of at least some of the original learned parameters and its corresponding LPS and is executed instead of the original.

Systems and methods for implementing learned parameter systems on a programmable integrated circuit

A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.

Method and apparatus for implementing a system-level design tool for design planning and architecture exploration

Systems and methods relating to a programmable circuit. The programmable circuit includes multiple sectors. Each sector includes configurable functional blocks, configurable routing wires, configuration bits for storing configurations for the functional blocks and routing wires, and local control circuitry for interfacing with the configuration bits to configure the sector. The programmable circuit may include global control circuitry for interfacing with the local control circuitry to configure the sector. Each sector may be independently operable and/or operable in parallel with other sectors. Operating the programmable circuit may include using the local control circuitry to interface with the configurations bit and configure the sector. Additionally, operating the programmable circuit may include using the global control circuitry to interface with respective local control circuitry and configure the sector.

Programmable circuit having multiple sectors

Systems and methods are provided herein for providing an NoC including a configurable array of nodes, where a node of the configurable array of nodes operates in a default operating mode until a replacement operating mode is triggered. For example, when an NoC is unconfigured, a latch bank may be initialized to 'clear,' such that no routing decisions are stored. This may enable a default operating mode where routing logic updates the latches' values as needed to implement required routing behavior in a dynamic fashion until configuration is performed.

Network-on-chip with fixed and configurable functions

Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.

Programmable logic device with integrated network-on-chip

An integrated circuit include multiple regions, wherein at least one region includes a control circuit. The control circuit receives a target voltage value to supply to the region that enables the region to operate at a target speed. The control circuit also receives a first criticality value of a first path of a design programmed in the region. The first criticality value is based on a first propagation time of the first path and a first allowable time to traverse the first path while enabling the region to operate at the target speed. The control circuit further instructs a power regulator to supply voltage to the region based at least in part on the target voltage value and the first criticality value. The integrated circuit also includes the power regulator communicatively coupled to the at least one region. The power regulator supplies power to the at least one region.

Regional design-dependent voltage control and clocking

A computer-aided design (CAD) tool may identify don't care bits in configuration data. The don't care bits in the configuration data may change polarity without affecting the functionality of the circuit design. The CAD tool may compute an error check code (e.g., parity bits for a two-dimensional parity check) and insert the error check code into the configuration data. As an example, the CAD tool may replace don't care bits in the configuration data with the error code. The configuration data may be stored in configuration memory cells on a programmable integrated circuit, thereby implementing the circuit design with the error code on the programmable integrated circuit. During execution, the programmable integrated circuit may execute error checking and detect and correct errors in the configuration data based on the embedded error code.

Methods and apparatus for embedding an error correction code in storage circuits

An integrated circuit device includes a first memory cell that stores data representative of configuration data when operating in a first mode, wherein the first memory cell stores data representative of user-accessible data when operating in a second mode. The integrated circuit device also includes a second memory cell that stores a value indicating whether the first memory cell is operating in the first mode or is operating in the second mode. The integrated circuit device further includes a switch coupled to the first memory cell and controlled by the second memory cell, wherein the switch provides a defined value to be read in place of the stored data of the first memory cell when the second memory cell stores the value indicating that the first memory cell is operating in the second mode.

Lutram dummy read scheme during error detection and correction

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Palo Alto, CA, United States of America

Herman Henry Schmit