International Business Machines Corporation

Herman Dietrich Dierks

Venkat Venkatsubra

Vinit Jain

Agustin Mena, Iii

Dirk Michel

James Brian Cunningham

Binh K Hua

Sivarama K Kodukula

Kiet Hien Lam

Satya Prakesh Sharma

Tai-Chien Daisy Chang

Jiandi A An

Claude Basso

Fabrice Jean Verplanken

Jean Louis Calvignac

Colin Beaton Verrilli

Natarajan Vaidhyanathan

Dwip N Banerjee

Christoph Raisch

Robert H Bell, Jr

Andrew Dunshea

Chih-Jen Chang

Philippe Damon

Jos Manuel Accapadi

Mysore Sathyanarayana Srinivas

Hong Lam Hua

Octavian Florin Herescu

Jan-Bernd Themann

William Stephen Carter

Mallesh K Lepakshaiah

Gregory Scott Althaus

Jean-Philippe Sugarbroad

Bernard A King-Smith

Jose Raul Escalera

Andres Herrera

Helmut Cossmann

William James Hymas

Jean-Philipe Sugerbroad

Agustin Mena Iii

Mechanisms are provided, in a data processing system comprising a host system and a network adapter, for processing received frames of data over a network connection. The mechanisms receive, in the host system from the network adapter, a plurality of frames of data. The mechanisms record, by the host system, for each frame in the plurality of frames, a header size associated with the frame over a current predetermined interval. The mechanisms determine, by the host system, a receive buffer address offset for receive buffers in the host system for a next predetermined interval based on the recorded header sizes of the plurality of frames over the current predetermined interval. In addition, the mechanisms configure, by the host system, the network adapter to utilize the receive buffer address offset to perform data transfers with the host system.

Memory transfer optimization of network adapter data placement when performing header-data split operations

A cache within a computer system receives a partial write request and identifies a cache hit of a cache line. The cache line corresponds to the partial write request and includes existing data. In turn, the cache receives partial write data and merges the partial write data with the existing data into the cache line. In one embodiment, the existing data is 'modified' or 'dirty.' In another embodiment, the existing data is &#x201c;shared.&#x201d; In this embodiment, the cache changes the state of the cache line to indicate the storing of the partial write data into the cache line.

Partial line cache write injector for direct memory access write

Mechanisms for controlling rollover or reset of hardware performance counters in the data processing system. A signal indicating that a rollover or reset of a first hardware performance counter has occurred is received and it is determined if the first hardware performance counter is analytically related to one or more second hardware performance counters based on defined ganged hardware performance counter sets. A signal is sent to each of the one or more second hardware performance counters in response to a determination that the first hardware performance counter is analytically related to the one or more second hardware performance counters. Each of the one or more second hardware performance counters is reset to an initial value in response to the one or more second hardware performance counters receiving the signal from the ganged hardware performance counter rollover/reset logic.

Ganged hardware counters for coordinated rollover and reset operations

An apparatus and method for an improved bulk read socket call are provided. With the apparatus and method, a new field, so_rcvlen, is added to the socket structure that identifies the bulk read size requested by the user. The kernel of the prior art recv( ) function is also modified so that it sets the so_rcvlen to the size requested by the user prior to the recv( ) function going to sleep and waiting for the full data size requested by the user. A new flag, SP_MSGWAITALL, is also provided in the socket structure. In the TCP input processing, when data is received for a particular socket, the current setting of the SP_MSGWAITALL is checked. If the SP_MSGWAITALL flag is set, it is determined whether the amount of data stored in the socket receive buffer is less than the value of so_rcvlen. If not, the TCP input processing does not wake up the recv( ) thread. However, for every alternate segment, the TCP input processing sends back an acknowledgment (ACK). In the TCP output processing, when the SP_MSGWAITALL flag is set and the amount of data in the socket receive buffer is less than so_rcvlen, the full window is advertised. Once the TCP input processing determines that there is at least an amount of data in the socket receive buffer equal to the value of so_rcvlen, the TCP input processing will wake up the recv( ) thread and the SP_MSGWAITALL flag is reset.

Method and apparatus for an improved bulk read socket call

A method, apparatus, and computer instructions for transferring data from a memory to a network adapter in a data processing system. The frame size for a transfer of the data from the memory to the network adapter is identified. If the frame size is divisible by a cache line size without a remainder, a valid data length is set equal to the length field. However, if the frame size divided by the cache line size results in a remainder, the length field is set to align the data with the cache line size. The data transfer is then initiated using these fields.

Method and apparatus for transferring data from a memory subsystem to a network adapter by extending data lengths to improve the memory subsystem and PCI bus efficiency

Scheduling threads in a multi-processor computer system including establishing an interrupt threshold for a thread, where the interrupt threshold represents a maximum permissible number of interrupts during thread execution on a processor; executing the thread on a current processor, where the thread has thread affinity for one or more processors including the current processor; counting a number of interrupts during execution of the thread on the current processor; and removing thread affinity for the current processor in dependence upon the counted number of interrupts and the interrupt threshold.

Scheduling threads in a multi-processor computer

A computer implemented method, apparatus, and computer usable code for receiving data from a sender across a network connection for the data transfer. An expected size for a congestion window for the sender is identified. An amount of the data received from the sender is tracked. An acknowledgment is sent in response to the amount of data received from the sender meet in the expected size of the congestion window for the sender.

Acknowledging packet receipt based on expected size of sender's congestion window

A system, method, and program product is provided that requests, by a first computer system, a new network session with a second computer system. The new network session request occurs after a previous network session between the two systems and the new network session request includes a new sequence number that is different from a previous sequence number that was used during the previous network session. The first computer system receives an acknowledgement from the second computer system that references the previous sequence number instead of the new sequence number. In response to receiving the acknowledgement at the first computer system that references the previous sequence number, the first computer system modifies the new sequence number by setting it to a value that is higher than the previous sequence number, and the first computer system re-requests the new network session using the modified new sequence number.

System and method for minimizing retry delays in high traffic computer networks

Mechanisms for processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission. Multiple hardware receive packet processors in the network adapter may be used, along with a flow classification engine, to route received data packets to appropriate receive queues and processing cores for processing.

Multicore communication processing

A computer implemented method, apparatus, and computer usable program code to determine whether an acknowledgment packet from an end point acknowledges receipt of unsent data in response to receiving the acknowledgement packet over a connection with the end point. A determination is made as to whether acknowledgement packets for unsent data have been received sequentially a selected number of times over the connection in response to the acknowledgement packet being for unsent data. The acknowledgment packet is dropped if acknowledgement packets have been received sequentially the selected number of times over the connection.

Method and apparatus for preventing network outages

A computer implemented method for receiving data from a sender across a network connection for the data transfer. An expected size for a congestion window for the sender is identified. An amount of the data received from the sender is tracked. An acknowledgment is sent in response to the amount of data received from the sender meet in the expected size of the congestion window for the sender.

TCP/IP method FPR determining the expected size of conjestion windows

A method, system and apparatus for improving network performance of a multiprocessor system that has a limited number of physical network interfaces by using virtual IP addresses are provided. When a processor of the multiprocessor system determines that it is processing network data, it uses a virtual IP address to transmit the data. The virtual IP address is associated with a buffer; and thus the data is sent to the buffer. This allows the processor to be free to process other data, network or otherwise. The buffer, with the help of a controller, then contends for the use of one of the limited physical network interfaces to transmit the data.

Apparatus and method of improving network performance using virtual interfaces

Method for transferring data from a memory subsystem to a network adapter by extending data lengths to improve the memory subsystem and PCI bus efficiency

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Round Rock, TX, United States of America

Herman Dietrich Dierks