Siemens Aktiengesellschaft

Siemens Ag Osterreich

Herbert Taucher

Martin Matschnig

Majid Ghameshlu

Thomas Hinterstoisser

Bernhard Fischer

Vladimir Zahorcak

Friedrich Eppensteiner

Christian Cech

Wilhelm Meyrath

Sebastian Geiger

Ulrich Hahn

Hannes Muhr

Dusan Tomic

A method for storing key data in an electronic component formed as an integrated programmable circuit, such as a field programmable gate array, which includes a base structure consisting of base elements, wherein configuration data is loaded, for each current program, onto the base elements and stored in a volatile matter, the key data is divided into key sub-data blocks, and a base element position is selected for each key sub-data block, where upon generating the configuration data for each current program or circuit function of the electronic component, selected base element positions of the key sub-data blocks are considered, while loading the configuration data, key sub-data blocks are stored in the base elements defined by selected base element positions, and after successfully programming the electronic component, the key sub-data blocks of base elements specified by selected base element positions are ascertained and assembled to form the key data.

Method for storing key data in an electronic component

A method for realizing an artificial neural network via an electronic integrated circuit (FPGA), wherein artificial neurons grouped into different interlinked layers for the artificial neural network, where a functional description is created for each neuron of the artificial neural network, taking into account a specifiable starting weighting, a synthesis is performed for each neuron based on the associated functional description with the associated specified starting weighting, a network list is determined as the synthesis result, in which at least a base element and a starting configuration belonging to the base element are stored for each neuron, a base element is formed as a lookup table (LUT) unit and an associated dynamic configuration cell, in which a current configuration for the LUT unit or the base element is stored, and where the network list is implemented as a starting configuration of the artificial neural network in the electronic integrated circuit.

Method for realizing a neural network

A system and method for the predictive maintenance of electronic components that includes sensors at at least one position via which present values of system parameters, such as temperature and voltage, and a signal propagation time at the at least one position are determined, where values of the system parameters and the signal propagation time presently determined by the sensors are retrieved by a central monitoring unit, an individual valid limit value is determined for the signal propagation time at each of the at least one position via the central monitoring unit based on the presently determined values of the system parameters, and the presently determined signal propagation time at each of the at least one position is compared with the associated valid limit value, and a notification is sent to a superordinate level, if the signal propagation time exceeds the limit value to trigger replacement of the electronic component.

Method and system for predictive maintenance of integrated circuits

A method for optimal arrangement of a random generator on an electronic component, which includes a programmable integrated circuit and a basic structure consisting of a plurality of basic blocks, wherein during an initialization phase, starting from a starting configuration for a respective current arrangement of the random generator, the following are performed with a predefined number of repetitions, i.e., a predefined test sequence is performed for the current arrangement of the random generator, a test result is forwarded to a reconfiguration module and the current arrangement on the electronic component is reconfigured via the reconfiguration module, where upon each repetition, the test result of the current arrangement of the random generator is compared with the test result of a previous arrangement, and the current arrangement is saved in the reconfiguration module, if the test result for the current arrangement has a better test result than the previous arrangement.

Method for optimal arrangement of a random number generator

A method for adjusting a pull resistor on a contact terminal of an electronic module arranged on a printed circuit board, in particular an ASIC, after initiating a restart of the electronic module which, during a run-up process, moves the electronic module from a switched-off state into a switched-on state, wherein after initiating a restart during the run-up process from a partial circuit arranged on the electronic module and operationally ready during the run-up process, adjustment information relating to a desired adjustment of the pull resistor is retrieved from a storage unit arranged on the printed circuit board outside of the electronic module and transmitted via a contact line between the electronic module and the storage unit, where the run-up process of the electronic module is only completed after successful adjustment of the respective pull resistor based on basis the retrieved adjustment information.

Method for adjusting pull resistors of an electronic module

A circuit arrangement and method for temporally limiting and separating access between at least one master unit and at least one slave unit via a network-on-a-chip bus system in a system-on-a-chip, wherein the access between the at least one master and slave units is implemented via communication paths defined by bus interfaces, where within the circuit arrangement, the network-on-a-chip bus system is expanded by an adaptation unit that includes an access manager and a complementary logic for the bus interfaces, where the adaptation unit and the bus interfaces are then controlled by the access manager via the complementary logic using a communication plan such that access between the master and slave units via the communication paths specified by bus interfaces is performed in accordance with the temporal requirements of the communication plan so that time-controlled systems can be implemented simply using commercially obtainable standard bus systems.

Method and circuit arrangement for temporally limiting and separately accessing a system on a chip

A method for protecting an integrated circuit against unauthorized access to key registers, wherein functions and/or applications of the integrated circuit are unlocked and/or activated via data stored in key registers, such as during the start-up of the integrated circuit and/or during ongoing operation, where if such a key register is accessed, the data word used to perform the access is compared with specified key data, and if access via a data word deviating from the specified key data is detected, the access is marked as unauthorized, the access marked as unauthorized is then recorded and evaluated, and after the analysis, appropriate protective measures are triggered to prevent further unauthorized access such that a key register method for protecting sensitive data is expanded in a simple manner and hacker attacks are quickly detected and thwarted.

Method for protecting an integrated circuit against unauthorized access

A method for a logic circuit including a plurality of components and channels which are each assigned functional properties in a circuit model to simulate how the logic circuit functions, where the circuit model, in a section of the method, is expanded by mechanisms for security analysis, and where in a further section of the method, the following method steps are implemented via a simulation unit, i.e., check whether the security property of the respective component and/or the respective channel corresponds to the security requirement of the security-relevant data and generate a security risk report if it does not correspond thereto, apply a modeled attack to a component and/or to a channel, and determine a vulnerability of the security property of the respective component and/or of the respective channel to the applied attack, and if there is vulnerability of the security property, generate an attack report.

Method for analyzing a logic circuit

A circuit arrangement and method for securing an integrated electronic circuit against scans of an address space, wherein the circuit arrangement has at least one master unit and at least one slave unit interconnected via a bus system for access of the master unit to the slave unit, and addresses are used from an address space that is allocated and used in accordance with functionalities of the integrated electronic circuit, where a defense slave unit is connected to the bus system, access to unused address regions of the address space are forwarded to the defense slave unit, the access is analyzed and evaluated by the defense slave unit and depending on an analysis result and the respective access type, defensive measures are triggered, such that address space scans are interrupted or a potential scan result is rendered useless in a simple manner.

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Moedling, Austria

Herbert Taucher