Burroughs, Inc.

Mosaic Systems, Inc.

Environmental Research Institute of Michigan

Herbert Stopper

Cornelius C Perkins

Richard A Flasck

George J Sprenkle

Raymond C Yuen

Robert E Braun

Mark A Menezes

William W Allen

Richard H Jones

A method and apparatus for optimizing the signal transmission speed between a signal source and a signal receiver of a microelectronic circuit is disclosed. The method includes the step of providing a signal transmission path whose length provides a predetermined ratio between its resistance and characteristic impedance which will reproduce the transmitted signal at the receiving end upon the first signal transition. The length of this transmission path may be increased by using a nonhomogeneous line structure in which the characteristic impedance increases in the direction of the signal transmission. In one form of the invention, the signal transmission path is formed by interconnecting a plurality of micro-strip conductors disposed on different planes of a universally programmable silicon circuit board. Under the appropriate circumstances, a signal can travel through such a 'semi-lossy' transmission path at approximately the speed of light.

Transmission lines for wafer-scale integration and method for increasing

Disclosed is a wafer scale device 10, 201 on which is formed a layer of thin film as an interconnection system 203 with contact sites 202, 207 between the interconnection system 203 and die bonding sites 202 of the wafer 10, 201 to form a monolithic wafer. The interconnection system 203 has bonding sites on the surface of the wafer 10, 201 to which chips 11 are bonded to form a hybrid monolithic wafer system. The wafer 10 is packaged within a wafer package, FIG. 4, and the packaging system utilizes a header 20 which is a flexible circuit connector between the wafer package and first level circuit board 30.

Wafer scale package system and header and method of manufacture thereof

Disclosed is a wafer substrate for integrated circuits 1 which by itself may be made either of conductive or non-conductive material. This substrate carries two planes or layers of patterned metal 19,20, thus providing two principal levels of interconnection. A programmable amorphous silicon insulation layer 21 is placed between the metal layers. There are sheet lower metal layers with an insulator which permit power distribution across the wafer. Connections between the metal layers or between the metal layer and the substrate can be made through via holes in the insulator layers or layers, respectively. Pedestals are provided for bonding.

Wafer and method of making same

A computer and switching mainframe connection system and flat cable connection elements therefor. The elements are a flat cable 'S' circuit, FIG. 1, and a bus circuit, FIG. 8. The 'S' circuit has an elongated run (68) and a 'S' portion (43). The bus circuit has 'U' elements (61) and a linear portion (58) with the signal lines of the 'U' elements (61) connected to the signal lines of the bus circuit (80). The mainframe is formed of an array of circuit boards (100) bearing a wafer (90) and header (99) for the wafer which in turn is connected to ports (101) to which tab connectors (57, 56, FIG. 3) of the bus circuit and 'S' circuit are connected.

Cable system

Disclosed is a substrate for an array of integrated circuit dice 10' disposed in a regular array on the monolithic wafer substrate 1. Also disposed on the wafer substrate 1, is a network 11'0 interconnecting various circuits 10', with other integrated circuits, disposed in the array formed on the wafer for data transfer therebetween. Terminals 12' exist in the network 11' for connection of the connections of the network with the various integrated circuits 10'. The networks are connected to a contact pad by one or more connection pads 13', for power and for data entry, and there is provided an auxiliary lead and contact pad for each network for testing each network for operability, also disclosed in the testing method.

Method of testing networks on a wafer having grounding points on its

Disclosed is a substrate for an array of integrated circuit dice 10' disposed in a regular array on the monolithic wafer substrate 1. Also disposed on the wafer substrate 1 is a network 11' interconnecting various circuits 10', with other integrated circuits, disposed in the array formed on the wafer for data transfer therebetween. Terminals 12', exist in the network 11' for connection of the connections of the network with the various integrated circuits 10'. The networks are connected to a contact pad by one or more connection pads 13', for power and for data entry, and there is provided an auxiliary lead and contact pad for each network for testing each network for operability, also disclosed in the testing method.

Wafer including test lead connected to ground for testing networks

Disclosed is a substrate for an array of integrated circuit dice 10' disposed in a regular array on the monolithic wafer substrate 1. Also disposed on the wafer substrate 1 is a network 11' interconnecting various circuits 10', with other integrated circuits, disposed in the array formed on the wafer for data transfer therebetween. Terminals 12' exist in the network 11' for connection of the connections of the network with the various integrated circuits 10'. The networks are connected to a contact pad by one or more connection pads 13', for power and for data entry, and there is provided an auxiliary lead and contact pad for each network for testing each network for operability, also disclosed in the testing method.

Wafer scale integrated circuit

Disclosed is a foldable circuit assembly 10 which has eight support members 11 having windows 12 in which circuits are bonded. The support members are all interconnected by a flexible polyimide web and an electrical circuit is etched thereon so as to interconnect the circuits and the external world via a contact tab extending from one of the support wafer members 11.

Foldable circuit assembly

Disclosed is a wafer substrate for integrated circuits (1) which by itself may be made either of conductive or non-conductive material. This substrate carries two planes or layers of patterned metal (19, 20), thus providing two principal levels of interconnection. An insulation layer (21) is placed between the metal layers and also between the lower metal layer and the substrate if the latter is conductive. Connections between the metal layers or between the metal layer and the substrate can be made through via holes in the insulator layer or layers, respectively. The real estate provided by the substrate (1) is divided up into special areas used for inner cells (2) outer cells (3) signal hookup areas (4) and power hookup areas (5). The cells are intended to host the integrated circuit chips (24, 25) and to provide the bonding pads (8) for the signal connections between the chips and the substrate.

Universal interconnection substrate

An In-Situ Test and Diagnostic Circuit and Method to monitor the integrity of external connections of a current mode logic integrated circuit chip (inputs and outputs) as well as the integrity of the logic function thereof. The circuit comprises three parts: an 'Open' Input Detector to detect open connections or connections that are becoming open between one chip and another; an Output Short Detector to monitor shorts at any chip output; and a Signature Test and Diagnostic circuit to determine if the logic function of the chip itself is operational. All the foregoing circuit parts are formed as an integral part of each CML chip and connected to an output terminal called a Test and Diagnostic Pin.

In-situ test and diagnostic circuitry and method for CML chips

An improved CML (Current Mode Logic) gate having voltage and temperature compensating means for maintaining output levels and input thresholds invariant with fluctations in supply voltage and junction temperature. The output of the compensating means, measured with respect to ground, will track variations in supply voltage on a one-to-one basis except that the output is allowed to vary by one V.sub.be with junction temperature. This output is supplied to the base of the constant-current source transistor which feeds the differential amplifier stage of the CML gate and to the base of a constant current source transistor whose collector is coupled to the base of the non-input transistor of the differential amplifier stage of the CML gate. The compensating circuitry includes an output transistor, resistive means for tracking variations in supply voltage, and a temperature compensation network having a temperature compensation factor of zero, both said resistive means and the output of said temperature compensation network are coupled to the base of the output transistor. The temperature compensation network achieves an overall compensation factor of zero by combining a temperature compensating subcircuit having a compensation factor of minus one with a temperature compensating subcircuit having a compensation factor of plus one via a unique voltage divider arrangement.

Voltage and temperature compensation circuitry for current mode logic

A system is described which provides for high density packaging of electronic equipment, particularly data processing systems. Subnanosecond integrated circuits of the LSI or MSI type in pluggable packages are adapted to be installed in receptacles or connectors. A cooling frame is provided which supports the package connectors as well as the package-to-package interconnection medium. In accordance with the system, groups of integrated circuit packages logically partitioned into functional elements and having, for example, gate complexities of the order of four thousand to ten thousand gates, comprise an island. The system may be expanded further by interconnecting several islands.

Growing community of inventors

Orchard Lake, MI, United States of America

Herbert Stopper