Infineon Technologies Ag

Siemens Aktiengesellschaft

Herbert Sch&auml;fer

Martin Franosch

Reinhard J Stengl

Hermann Wendt

Hans Reisinger

Volker Lehmann

Gerrit Lange

Josef Willer

Lothar Risch

Wolfgang Klein

Thomas Meister

Thomas Peter Haneder

Gerhard Beitel

Bernhard Lustig

Harald Bachhofer

Wolfgang H&ouml;nlein

Ulrike Gr&uuml;ning

Josef B&ouml;ck

Stephan Schlamminger

The bipolar transistor is produced such that a connection region of its base is provided with a silicide layer, so that a base resistance of the bipolar transistor is small. No silicide layer is produced between an emitter and an emitter contact and between a connection region of a collector and a collector contact. The base is produced by in situ-doped epitaxy in a region in which a first insulating layer is removed by isotropic etching such that the connection region of the base which is arranged on the first insulating layer is undercut. In order to avoid defects of a substrate in which the bipolar transistor is partly produced, isotropic etching is used for the patterning of auxiliary layers, whereby etching is selective with respect to auxiliary layers lying above, which are patterned by anisotropic etching.

Method for fabricating a bipolar transistor and method for fabricating an integrated circuit configuration having such a bipolar transistor

A MOS transistor and a method for fabricating the same include producing a well doped by a first conductivity type in a semiconductor substrate. An epitaxial layer having a dopant concentration of less than 10 cm is disposed on a surface of the doped well. Source/drain regions doped by a second conductivity type, opposite to the first conductivity type, and a channel region, are disposed in the epitaxial layer, and their depth is less than or equal to the thickness of the epitaxial layer. A method for fabricating two complementary MOS transistors is also provided.

MOS transistor, method for fabricating a MOS transistor and method for fabricating two complementary MOS transistors

A DRAM capacitor is described that contains a BaSrTiO (BST) dielectric. The dielectric has a three-layer structure enabling the formation of a potential trough in which electrons can be permanently trapped.

DRAM memory capacitor having three-layer dielectric, and method for its production

A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is used for the electrodes. Suitable materials for the electrodes are metals such as platinum, tungsten and iridium or silicides.

Storage capacitor for a DRAM

A memory cell configuration in a semiconductor substrate is proposed, in which the semiconductor substrate is of the first conductivity type. Trenches which run parallel to one another are incorporated in the semiconductor substrate, and first address lines run along the side walls of the trenches. Second address lines are formed on the semiconductor substrate, transversely with respect to the trenches. Semiconductor substrate regions, in which a diode and a dielectric whose conductivity can be changed are arranged, are located between the first address lines and the second address lines. A suitable current pulse can be used to produce a breakdown in the dielectric, with information thus being stored in the dielectric.

Electrically programmable non-volatile memory cell configuration

A manufacturing method for a capacitor in an integrated memory circuit includes initially depositing a first conducting layer and an auxiliary layer acting as an etch-stop onto a carrier. Then a layer sequence which contains alternating layers of the first material and a second material is produced on top of the first conducting layer and the auxiliary layer. The layer sequence may, in particular, have p,/p,silicon layers or silicon/germanium layers. A layer structure with a base of a capacitor to be produced is formed from the layer sequence. Sides of the layer structure are provided with a conducting supporting structure. An opening is formed inside the layer structure, all the way down to the auxiliary layer and then the auxiliary layer and the layers made of the second material are removed. A free surface of the layers made of the first material and the supporting structure are provided with a capacitor dielectric onto which a counter electrode is applied.

Manufacturing method for a capacitor in an integrated memory circuit

An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.

Integrated electrical circuit having at least one memory cell and method for fabricating it

Growing community of inventors

Höhenkirchen-Siegertsbrunn, Germany

Herbert Schäfer

Growing community of inventors

Höhenkirchen-Siegertsbrunn, Germany

Herbert Sch&auml;fer

Herbert Schäfer