Infineon Technologies Ag

International Business Machines Corporation

Siemens Aktiengesellschaft

Kabushiki Kaisha Toshiba

Infineon Technologies Flash Gmbh & Co. Kg

Ingentix Gmbh & Co. Kg

Herbert Palm

Josef Willer

Herbert Lei Ho

David M Dobuzinsky

James F Moseman

Philip L Flaitz

Hiroshi Takato

Michael Smola

Andreas Kux

Seiko Yoshida

John Preston Benedict

Hans W Poetzlberger

Erwin N Hammerl

Lawrence Alfred Clevenger

Kenneth Parker Rodbell

Ronald G Filippi

Hans Taddiken

Christoph Ludwig

Mark Hoinkis

Mark A Jaso

Robert Reiner

Atul Champaklal Ajmera

Achim Gratz

Roy Charles Iggulden

Erwin Hammerl

Armin Kohlhase

Michael Bollu

Mayk Roehrich

Florian Schnabel

Frank Puschner

Jakob Kriz

Stefan Weber

Samuel C Ramac

Jurgen Fischer

Stephen G Fugardi

Stefan Wallstab

Eric-Roger Brücklmeier

Erdmute Wohlrab

Jeffery L Hurd

Ebrahim A Mehter

In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

Semiconductor memory having charge trapping memory cells and fabrication method

Data carrier card having a card body of a flat form and having a recess, a carrier, a chip arranged on the carrier and inserted in the recess of the card body, external contact elements arranged on the carrier and electrically connected to the chip via conductor runs, and a cover covering the recess in operative connection with the carrier such that the carrier is held along the bottom in the recess, wherein the external contact elements and the chip are arranged on a same side of the carrier.

Data carrier card

An individual configuration contains at least a first structure and a second structure, which are aligned with respect to each other. A position sensing device that senses a relative position of the first structure with respect to the second structure, in order to establish that a manipulation has been performed on the configuration, is provided.

Individual configuration

The access time for the use of an electronic device, for example a chip, is prolonged after each unauthorized access attempt. The access time is determined by the time for the matching of the turn-on voltages of two floating gate cells. Before an access attempt, the turn-on voltage of one cell is set to a predefined initial value and the turn-on voltage of the other cell is set to a value which is higher in comparison and which is increased after each unauthorized access.

Circuit and method for protecting electronic devices

A time recording device employs a floating gate cell, wherein an ON layer structure or an ONO layer structure is provided between floating gate and control gate. A charge injection unit is provided to inject charges into the floating gate electrode and into the nitride layer of the ON structure or the ONO structure by applying a voltage or voltage pulses to the control gate electrode, a center of concentration of the charges injected into the nitride layer being located at the interface between oxide layer and nitride layer of the layer sequence. The time recording device also includes a unit for recording a time which has elapsed since charge injection on the basis of changes in the transmission behavior of the channel region caused by a shift in the center of concentration of the charges in the nitride layer away from the interface.

Time recording device and a time recording method employing a semiconductor element

A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.

Device interconnection

Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain region that are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by a dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode, there is an oxide-nitride-oxide layer sequence. The layer sequence is provided for the purpose of trapping charge carriers at the source and the drain.

Memory cell, memory cell configuration and fabrication method

An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged on the source/drain regions of memory transistors having an ONO memory layer sequence and gate electrodes that are arranged in trenches. The metal silicide is preferably cobalt silicide, and the metal-containing layer is preferably tungsten silicide or WN/W.

Method for fabricating a memory cell

An integrated memory circuit of the type of an NROM memory includes recessed bit lines formed of a material having a low ohmic resistance. By recessing the bit lines with respect to the semiconductor substrate surface of a peripheral controlling circuit for an array of memory cells allows to form the word line lithography on a perfect or almost perfect plane so that the word line formation results in a production with higher yield and, therefore, lower costs for the individual integrated memory circuit.

NROM memory circuit with recessed bitline

A circuit configuration with a deactivatable scan path, includes a number of function blocks each connected to at least one other of the function blocks. At least one sub-set of the connections is in the form of a respective interlocking element which can be switched through an activation line (Scan Enable) from a normal mode to a test mode and which has a further data input and data output. The further data inputs and outputs are connected to one another by data line sections in such a manner that the interlocking elements form a shift register which provides a scan path. At least one electrically programmable protection element, which either interrupts a given line or connects it to a defined potential, is disposed along the activation line (Scan Enable) and/or the data line sections.

Circuit configuration with deactivatable scan path

Memory cell, memory cell arrangement and fabrication method

The power supply device has a temporary energy store, a main energy store, and a switching device. The switching device has three switching states. The temporary energy store is connected in the first switching state to a power supply input and is connected in the second switching state to the main energy store, which is connected to a power supply output. An energy discharge device is connected to the temporary energy store in the third switching state of the switching device which follows directly the second switching state.

Circuit configuration having a multi-state switching device and an energy discharge device connected to a temporary energy storage device in a third switching state of the switching device

Disclosed is an improved process and liner for trench isolation which includes either a single oxynitride layer or a dual oxynitride (or oxide)/nitride layer. Such a process and liner has an improved process window as well as being an effective O.sub.2 diffusion barrier and resistant to hot phosphoric and hydrofluoric acids.

Shallow trench isolation with oxide-nitride/oxynitride liner

A method of forming aluminum contacts of submicron dimensions wherein, after formation of both vias and line openings in a silicon oxide layer, a metal stop layer is deposited, followed by deposition of aluminum. Alternatively, the metal stop layer is deposited prior to forming the vias and line openings. The excess aluminum is removed by chemical-mechanical polishing, the stop layer providing high selectivity to the chemical mechanical polishing. The stop layer is then removed. The resultant silicon oxide-aluminum surface is planar and undamaged by the chemical-mechanical polishing step.

Method of making an aluminum contact

Growing community of inventors

Höhenkirchen, Germany

Herbert Palm