Sun Microsystems, Inc.

Apple Inc.

Herbert Lopez-Aguado

Gary R Lauterbach

Denise Chiacchia

Peter A Mehring

William C Athas

William L Lynch

Jung Wook Cho

Conrad Havluj Ziesler

Thomas Y Ho

A system and method for efficiently synchronizing multiple processing cores on a system-on-a-chip (SOC). A SOC includes an interrupt controller and multiple processing cores. The interrupt controller includes a main time base counter. The SOC includes multiple local time base counters, each coupled to a respective one of the processing cores. Synchronization logic blocks are used to update the local counters. These blocks receive a subset of bits from the interrupt controller. The subset of bits represents a number of least significant bits of the main counter less than a total number of bits for the main counter. The logic blocks update an associated local counter according to changes to the received subset of bits. A difference may exist between values of the main counter in the interrupt controller and the local counter in the processing core. However, this difference may be a constant value.

Controller core time base synchronization

A system that determines power consumption on an IC chip. The system includes a test structure located within the IC chip variations which includes one or more gates which receives power from a power source, wherein each gate has a different drive strength, and wherein the output of each gate is coupled to a load through a corresponding switch. The system also includes a current-measuring mechanism coupled to the power supply which measures the current consumed by the gates. When a specific switch is activated, the output of a corresponding gate is coupled to the load, thereby causing the corresponding gate to drive the load. The current consumed by the corresponding gate is measured by the current measuring mechanism. The measured current can be used to determine the power consumption of the corresponding gate driving the load.

Method and apparatus for measuring die-level integrated circuit power variations

A central processing unit of a computer includes a single-ported data cache and a dual-ported prefetch cache. The data cache accommodates a first pipeline and the prefetch cache, which is much smaller than the data cache, accommodates both the first pipeline and a second pipeline. If a data cache miss occurs, a row of data corresponding to the specified address is stored in the data cache and the prefetch cache. Thereafter, if a prefetch cache hit occurs, a row of data corresponding to a prefetch address is loaded into the prefetch cache. The prefetch address may, for instance, be generated by adding a fixed increment to the specified address. This operation frequently results in the prefetch cache storing data soon requested by a computer program. When this condition is achieved, the data corresponding to the subsequent address request is rapidly retrieved from cache memory without incurring memory latencies associated with the external cache, the primary memory, and the secondary memory. In this manner, the prefetch cache of the present invention facilitates improved memory latencies. Further, the prefetch cache allows for two data requests to be processed simultaneously without a corresponding two-fold increase in cost of data cache memory.

Microprocessor having a prefetch cache

A central processing unit (CPU) of a computer has a data caching unit which includes a novel dual-ported prefetch cache configured in parallel with a conventional single-ported data cache. If a data cache miss occurs, the requested data is loaded into the data cache and into the prefetch cache. Thereafter, each data request which results in a prefetch cache hit triggers the prefetching of data into the prefetch cache. A data load history tracking circuit maintains a running history of instructions that request data from external memory, and uses the resulting loop heuristics of these instructions to generate a stride. The stride is used to derive a prefetch address which identifies data that is predicted to be soon requested in subsequent instructions. Data corresponding to the prefetch address is then loaded into the prefetch cache. Thus, where a subsequent instruction requests data which has been prefetched into the prefetch cache, latencies associated with external memory may be hidden, thereby increasing the data bandwidth of the CPU.

Apparatus and method for generating a stride used to derive a prefetch

A central processing unit (CPU) of a computer has a data caching unit which includes a novel dual-ported prefetch cache configured in parallel with a conventional single-ported data cache. In response to a data cache miss, the requested data is fetched from external memory and loaded into the data cache and into the prefetch cache. Thereafter, if a prefetch cache hit occurs, the physical address of the corresponding data request is provided to a prefetch engine which, in turn, adds a stride to the physical address to derive a prefetch address. This prefetch address identifies data which is predicted to be soon requested in subsequent instructions of the computer program. Data corresponding to the prefetch address is then retrieved from external memory and loaded into the prefetch cache. This prefetching operation frequently results in the prefetch cache storing data that is requested by subsequently executed instructions in a computer program. When this condition occurs, data is immediately retrieved from the prefetch cache and provided to execution units within the CPU, thereby eliminating latencies associated with external memory.

A central processing unit (CPU) of a computer includes a novel prefetch cache configured in parallel with a conventional data cache. If a data cache miss occurs, the requested data is fetched from external memory and loaded into the data cache and into the prefetch cache. Thereafter, if a prefetch cache hit occurs, a prefetch address is derived, and data corresponding to the prefetch address is prefetched into the prefetch cache. This prefetching operation frequently results in the prefetch cache storing data that is requested by subsequently executed instructions in a computer program, thereby eliminating latencies associated with external memory. A software compiler of the computer ensures the validity of data stored in the prefetch cache. The software compiler alerts the prefetch cache that data stored within the prefetch cache is to be rewritten and, in response thereto, the prefetch cache invalidates the data. In this manner, data may be invalidated without requiring use of conventional cache snooping mechanisms, thereby increasing the speed with which data in cache memory may be invalidated. The ability to more quickly invalidate data in cache memory allows data previously considered 'non-cachable' to be stored, and remain valid, in cache memory.

Method for invalidating data identified by software compiler

A system and method for performing conditionally cache allocate operations to a data cache in a computer system. As supervisor mode operations typically do not experience data locality of accesses frequently found in user mode operations, it has been determined that performance benefits can be achieved by inhibiting cache allocate operations during supervisor mode. When a write miss to the cache occurs, the memory management unit checks the state of the processor status register to determine the mode of the processor. If the processor status register indicates that the processor is in supervisor mode, the memory management unit issues a signal to the data cache controller that the data is non-cacheable. When the data cache controller receives a non-cacheable signal, the cache allocate process is not performed. The non-cacheable signal is issued by the memory management unit while the processor is in supervisor mode regardless of the state of the cacheable status bit associated with the memory. Thus, if the processor is not in supervisor mode, the memory management unit will issue a non-cacheable signal to-the data cache controller based upon the state of the cacheable status bit associated with the memory. This status bit is typically found in the corresponding page table entry in the page table of a translation look aside buffer. Therefore, although a supervisor mode operation inhibits a cache allocate operation, subsequent non-supervisor mode operations to the same data will proceed based upon the state of the cacheable status bit associated with the memory.

Method and apparatus for optimizing supervisor mode store operations in

A translation look aside buffer including virtual page table pointer tags provides a system and method for accessing page table entries in page memory of the translation look aside buffer with decrease latencies caused by accesses to increasing levels of page tables during a table walk of the page table. Virtual tags identifying page table pointers at a predetermined level of the page table higher than the initial context level of the page table are included in the tag memory of the translation look aside buffer. These virtual tags provide a pointer which directly points to the page table pointer at that predetermined level of the page table. Therefore, if a TLB miss occurs wherein a tag for a page table entry corresponding to the virtual address is not found, a comparison is performed to determined if a corresponding virtual tag PTP is located in the tag memory. If the corresponding virtual tag PTP is found in the tag memory, access is gained to the PTP in the page table without the need for performing a time consuming table walk through the lower levels of the page table.

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Sunnyvale, CA, United States of America

Herbert Lopez-Aguado