International Business Machines Corporation

Siemens Aktiengesellschaft

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Other

Kabushiki Kaisha Toshiba

Infineon Technologies North America Corp.

Infineon Technologies Ag

Herbert Lei Ho

Jack Allan Mandelman

Kangguo Cheng

David M Dobuzinsky

Babar Ali Khan

Geng Wang

John Edward Barth, Jr

Subramanian Srikanteswara Iyer

Paul Christian Parries

Carl John Radens

Kirk David Peterson

Ramachandra Divakaruni

Kern Rim

Ali Khakifirooz

Reinaldo Ariel Vega

Qiqing Christine Ouyang

Ravi Mahendra Todi

Rishikesh Krishnan

Jeffrey P Gambino

Brent A Anderson

Vijay Narayanan

Qizhi Liu

Vibhor Jain

Michael Patrick Chudzik

Eduard Albert Cartier

John Joseph Pekarik

Reinhard J Stengl

Johnathan E Faltermeier

Vidhya Ramachandran

Robert Hannon

Karen A Nummy

Edward J Nowak

Tak H Ning

Chengwen Pei

Ravikumar Ramachandran

Gary Bela Bronner

Byeong Yeol Kim

Nicolas L Breil

Kevin R Winstel

Deok-kee Kim

Claude Ortolland

Ricardo Alves Donaton

Bruce Bennett Doris

Takashi Ando

Huilong Zhu

Shom Ponoth

Steven M Shank

Judson Robert Holt

Andres Bryant

Xiangdong Chen

Douglas Duane Coolbaugh

Chandrasekharan Kothandaraman

Martin Michael Frank

Thomas W Dyer

Bomy A Chen

Vamsi Krishna Paruchuri

Dae-Gyu Park

David Edward Kotecki

Rama Divakaruni

Jin Ping Liu

Scott David Halle

Naim Moumen

Oh-Jung Kwon

Stephan Alan Cohen

Kehan Tian

Mark A Jaso

Anthony K Stamper

John J Ellis-Monaghan

Mukta G Farooq

Arne Watson Ballantine

Davood Shahrjerdi

Ping-Chuan Wang

Zhong-Xiang He

Robert Mark Rassel

Louis Lu-Chen Hsu

Laertis Economikos

Brian Joseph Greene

Wayne Frederick Ellis

Tze-Chiang Chen

Hyun K Lee

Randy William Mann

Yun-Yu Wang

Roger Allen Booth, Jr

Jochen C Beintner

Wesley Charles Natzle

Ebenezer E Eshun

Viorel C Ontalus

Kwong Hon Wong

James Gardner Ryan

Hiroyuki Akatsu

Kenneth Jay Stein

Deok-Kee Kim

Hongwen Yan

Alvin Wayne Strong

Dan Moy

John Matthew Safran

Colin J Brodsky

Ephrem G Gebreselasie

Chienfan Yu

Troy Lawrence Graves-Abe

The present disclosure relates to semiconductor structures and, more particularly, to virtual bulk in semiconductor on insulator technology and methods of manufacture. The structure includes a heterojunction bipolar transistor formed on a semiconductor on insulator (SOI) wafer with a doped sub-collector material in a buried insulator region under a semiconductor substrate of the SOI wafer.

Virtual bulk in semiconductor on insulator technology

The present disclosure relates to semiconductor structures and, more particularly, to a device with a marker layer and methods of manufacture. The device includes: a collector region; an intrinsic base region above the collector region; an emitter region comprising emitter material and a marker layer vertically between the intrinsic base region and the emitter material; and an extrinsic base region in electrical contact with the intrinsic base region.

Heterojunction bipolar transistor with marker layer

The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region in electrical connection to the sub-collector region; an emitter located adjacent to the collector region and comprising emitter material, recessed sidewalls on the emitter material and an extension region extending at an upper portion of the emitter material above the recessed sidewalls; and an extrinsic base separated from the emitter by the recessed sidewalls.

Heterojunction bipolar transistor

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

Complementary transistor structures formed with the assistance of doped-glass layers

A method of making a semiconductor device includes disposing a mask on a substrate; etching the mask to form an opening in the mask; etching a trench in the substrate beneath the opening in the mask; and implanting a dopant in an area of the substrate beneath the opening of the mask, the dopant capable of gettering mobile ions that can contaminate the substrate; wherein the dopant extends through the substrate from a sidewall of the trench and an endwall of the trench.

Implant after through-silicon via (TSV) etch to getter mobile ions

A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.

Non-volatile memory device employing a deep trench capacitor

A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.

Trench metal insulator metal capacitor with oxygen gettering layer

The present disclosure generally relates to semiconductor structures and, more particularly, to a deep trench capacitor, integrated structures and methods of manufacture. The structure includes: a conductive material formed on an underside of an insulator layer and which acts as a back plate of a deep trench capacitor; an inner conductive layer extending through the insulator layer and an overlying substrate; and a dielectric liner between the inner conductive material and the conductive material, and formed on a sidewall of an opening within the insulator layer and the overlying substrate.

Deep trench capacitor with metal plate

Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions.

Dummy gate structure for electrical isolation of a fin DRAM

After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures. Optionally, selective deposition of a semiconductor material can be performed to form raised source and drain regions. In this case, the raised source regions grow only from the first sidewalls and do not grow from the second sidewalls. The raised source regions can be employed as a part of an etch mask during formation of the strap cavities. The strap structures are formed as self-aligned structures that are electrically isolated from adjacent access transistors by the dielectric spacers.

Dynamic random access memory cell with self-aligned strap

Method of forming a deep trench capacitor are provided. The method may include forming a deep trench in a substrate; forming a metal-insulator-metal (MIM) stack within a portion of the deep trench, the MIM stack forming including forming an outer electrode by co-depositing a refractory metal and silicon into the deep trench; and filling a remaining portion of the deep trench with a semiconductor.

DT capacitor with silicide outer electrode and/or compressive stress layer, and related methods

Trench metal-insulator-metal capacitor with oxygen gettering layer

Methods of forming polysilicon-filled deep trenches for an eDRAM are provided. The method may include forming a plurality of polysilicon-filled deep trenches in a substrate. An epitaxy-retarding dopant is introduced to an upper portion of the trenches. A plurality of fins are then formed over the substrate, with each polysilicon-filled deep trench including a corresponding fin extending thereover. A silicon layer is epitaxially grown over at least the polysilicon-filled deep trench. The dopant in the polysilicon-filled deep trenches acts to control the epitaxial growth of the silicon layer, diminishing or preventing shorts to adjacent fins and/or deep trenches at advanced technology nodes.

Controlling epitaxial growth over eDRAM deep trench and eDRAM so formed

Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.

Changing effective work function using ion implantation during dual work function metal gate integration

Growing community of inventors

Cornwall, NY, United States of America

Herbert Lei Ho