Lsi Corporation

Lsi Logic Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Herbert Johannes Preuthen

Stefan G Block

Juergen Dirks

Matthias Dinter

Ulrich G Hensel

Claus Pribbernow

Stephan Habel

Farid Labib

Johann Leyrer

Christian Haufe

Fulvio Pugliese

Jürgen Dirks

Hermann Sauter

Aspects of the disclosure provide a semiconductor device and method of manufacturing. Embodiments of the disclosure enable placing of protective structures without modifying spacing rules. The device includes a first device region defined above a substrate, the first device region being isolated from the substrate by a buried insulating layer. The first device region includes a first power rail, a first signal line traversing at least a first portion of the first device region, and a first plurality of edge cells positioned in the substrate adjacent the first device region. A first edge cell includes a substrate contact connecting the first power rail to the substrate and a first signal line antenna diode connecting the first signal line to the substrate.

Edge cell signal line antenna diodes

The disclosure provides transistor cells for integrated circuits and methods to form the same. A transistor cell according to the disclosure may include a substrate region including width between a first end and a second end, and a length between a third end and a fourth end in a direction orthogonal to the width. A first doped well (FDW) within the substrate region may be oppositely doped and may extend from the first end to a first interior boundary between the first and second ends of the substrate region, and from the third end to a second interior boundary between the third and fourth ends. A second doped well (SDW) within the substrate region may extend from the second end to a third interior boundary between the first and second ends, and the fourth end to a fourth interior boundary between the third and fourth ends.

Transistor cell for integrated circuits and method to form same

Structures for a circuit including field-effect transistors and methods for fabricating and operating such circuits. A plurality of logic cells with a first well and a second well. The first well is directly connected with ground. A tap cell includes an inverter having an output connected with the second well. The inverter is configured to provide a bias voltage having a first state in which a positive voltage is supplied to the second well and a second state in which the second well is connected with ground.

Simplified bias scheme for digital designs

The present disclosure provides a placing and routing method for implementing back bias in fully depleted silicon-on-insulator. In accordance with some illustrative embodiments herein, the placing and routing method comprises placing a first plurality of a standard tap well cell along a first direction, the standard tap well cell being formed by: routing a p-BIAS wire VPW and an n-BIAS wire VNW in a first a first metallization layer, and routing a power rail and a ground rail in a second metallization layer, the VPW and the VNW extending across each of the power and ground rail, wherein the VPWs of the first plurality of standard tap well cells are continuously connected and the VNWs of the first plurality of standard tap well cells are continuously connected.

Placing and routing method for implementing back bias in FDSOI

A storage medium for use in a computer to develop a circuit design. The storage medium recording a software tool that may be readable and executable by the computer. The software tool generally includes the steps of (A) receiving a first user input that identifies a specific cell of a plurality of existing cells in the circuit design, the specific cell having a timing characteristic, (B) generating a replacement display corresponding to the specific cell, the replacement display comprising a plurality of alternate cells suitable to replace the specific cell, each of the alternate cells having a different value associated with the timing characteristic of the specific cell, (C) receiving a second user input that identifies a replacement cell of the alternate cells and (D) automatically generating a first engineering change order to replace the specific cell with the replacement cell.

Timing violation debugging inside place and route tool

Disclosed herein is a multi-clock interface, an integrated circuit and a module thereof having the multi-clock interface and a library having cells corresponding to the above noted circuitry. In one embodiment the multi-clock interface includes: (1) a multi-clock reset synchronizer configured to receive a first external clock signal and a second external clock signal that is a multiple of the first clock signal, the reset synchronizer configured to synchronize a reset of both the first and second external clock signals and based thereon generate a reset release signal and (2) a multi-phase clock generator configured to receive the reset release signal and the second clock signal, the multi-phase clock generator configured to generate multiple clock phases from the second clock signal based on the reset release signal.

Clock tree insertion delay independent interface

An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional use of the integrated circuit, and cannot be aggressors on the data signals that are carried by the data lines that are used during the functional use of the integrated circuit. In addition, these non-switching output lines can act as guard traces that run between the data lines, further electrically isolating the data lines from one another. Further, because they do not switch during functional use of the integrated circuit, the overall power consumption of the integrated circuit is reduced.

Test pin gating for dynamic optimization

A circuit which includes an IP cell having a function select input signal line, combinatorial logic having an output connected to the function select input signal line of the IP cell, a configuration register having an output connected to an input of the combinatorial logic, wherein a high/low input signal line is also connected to the combinatorial logic, wherein the circuit provided that the configuration register receives configuration data during a start-up sequence, and configuration data is held by the combinatorial logic as the configuration register powers down during a functional mode.

Config logic power saving method

A method for establishing standard cell power connections is disclosed. The method generally includes the steps of (A) calculating a power consumption of a plurality of logic cells receiving power directly from a power rail, (B) removing at least one excess via from a plurality of vias directly connecting the power rail to a power mesh in response to the power consumption and (C) routing a signal through an area where the at least one excess via was removed.

Advanced standard cell power connection

An apparatus comprising a plurality of input cells, two or more local tie up cells, and two or more local tie down cells. The plurality of input cells may be configured to provide (i) one or more gate voltage signals and (ii) one or more supply voltage signals. The two or more local tie up cells may be configured to provide electrostatic discharge (ESD) protection to one or more first standard cells. Each of the local tie up cells may be coupled to (i) the one or more first standard cells and (ii) each of the gate voltage signals. The two or more local tie down cells may be configured to provide ESD protection to one or more second standard cells. Each of the local tie down cells may be coupled to (i) the one or more second standard cells and (ii) each of the supply voltage signals.

Automatic placement based ESD protection insertion

A method and apparatus for managing a plurality of change orders for a circuit design is disclosed. The method generally includes the steps of (A) receiving the change orders generated manually by a user, (B) analyzing the circuit design with all of the change orders implemented and (C) generating a report suitable for the user to understand based on a result of the analyzing.

Engineering change order scenario manager

A method for developing a circuit design is disclosed. The method generally include the steps of (A) generating a violation display based on violation information provided from a place-and-route tool and (B) generating a layout display based on layout information provided from the place-and-route tool. The violation display may include (i) a plurality of performance violations for the circuit design and (ii) a plurality of user inputs each associated with one of the performance violations. The layout display may include a layout view of the circuit design. The layout view may highlight at least one of (i) a plurality of cells and (ii) a plurality of networks each along a path related to a particular one of the performance violations identified by a user through the user inputs.

Growing community of inventors

Dorfen, Germany

Herbert Johannes Preuthen