David Sarnoff Research Center, Inc.

Herbert H Taylor

Danny Chin

Joseph E Peters, Jr

James Timothy Kaba

An apparatus and a method for combining the characteristics of both single instruction, multiple data stream (SIMD) and multiple instruction, multiple data stream (MIMD) computer architectures into a single parallel processing computer for performing multiple instruction stream processing. Such a parallel processing computer simultaneously performs both MIMD and SIMD operations on various processors within the computer. Additionally, at specified points during program execution, certain processors, i.e., a subset of all the processors, are synchronized. Once synchronized, the processors can exchange data. Moreover, the processors that do not take part in the synchronization continue executing instructions without interruption. The apparatus and method disclosed find applicability in video servers, medical imaging, special effects and animation and location based entertainment systems among other applications.

Parallel processing computer containing a multiple instruction stream

A processor within a parallel processing computer having a plurality of processors, where each processor is directly connected to a local storage memory. Each processor contains a principal processing element (PPE), a memory controller, and a multiplexor. The PPE executes a series of program instructions including local storage memory access instructions that cause the PPE to produce a local storage memory access request for accessing information within the local storage memory. The memory controller is connected to the PPE and a plurality of information resources of the parallel processing computer. This controller selectively routes local storage memory access requests from the information resources to an output port of the memory controller and generates an enable flag that is set to a first state when a selected one of the plurality of information resources can access the local storage memory and is set to a second state when the PPE is accessing the local storage such that access by the information resources is deferred until access by the PPE is complete. The multiplexor is connected to the PPE, the memory controller and the local storage memory. The multiplexor, operating in response to the enable flag, multiplexes the PPE access request with the selected information resource access requests such that access by the PPE to the local storage memory occurs substantially without time-delay interruption of the execution of program instructions by the PPE.

Method and apparatus for accessing local storage within a parallel

In a parallel processing computer containing a plurality of processors, each connected to a memory unit, a method and apparatus for accessing a distributed data buffer. Each of the processors within the computer executes a first routine for processing input data to generate output data. During processing, some or all of the data associated with the processing is temporarily stored within a predefined portion of each of the memory units that form a portion of the distributed data buffer. Upon occurrence of an interrupt signal, execution of the first routine is halted. Also, the status of the computer at the time the interrupt signal occurred is stored in memory. Thereafter, a second routine (an interrupt routine) is executed to access the data stored in the data buffer. Once the data is accessed, the status of the computer is restored in accordance with the previously stored computer status information. Lastly, the first routine is restarted at a position therein at which the first routine was interrupted to execute the second routine.

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Pennington, NJ, United States of America

Herbert H Taylor