Motorola Corporation

United States of America As Represented by the Secretary of the Air Force

Other

Freescale Semiconductor,inc.

Everspin Technologies, Inc.

Herbert Goronkin

Saied N Tehrani

Jun Shen

X Theodore Zhu

Xiaodong T Zhu

Raymond K Tsui

Vijay K Nair

George N Maracas

Kumar Shiralagi

Eugene Youjun Chen

Lawrence N Dworsky

Michael S Lebby

Jon Michael Slaughter

Jonathan K Abrokwah

William J Ooms

Carl Lynn Shurboff

Rimantas L Vaitkus

Anatoli A Korkin, Legal Representative

Martin Walther

Nicholas David Rizzo

Robert C Kane

Donald E Ackley

Mark A Durlam

Robert T Smith

Frederic Zenhausern

Jenn-Hwa Huang

Ronald N Legge

Ernest Schirmann

Wayne Frasch

Marino J Martinez

Theodore Zhu

Kathleen Anne Tobin

Richard Nguyen

Nada El-Zein

Lars Chapsky

Chia Fu Chou

Richard W Aldrich

Nada El Zein

Bradlfy N Engel

Ruth Y Zhang

A multi-state magnetoresistive random access memory device having a pinned ferromagnetic region with a magnetic moment vector fixed in a preferred direction in the absence of an applied magnetic field, a non-ferromagnetic spacer layer positioned on the pinned ferromagnetic region, and a free ferromagnetic region with an anisotropy designed to provide a free magnetic moment vector within the free ferromagnetic region with N stable positions, wherein N is a whole number greater than two, positioned on the non-ferromagnetic spacer layer. The number N of stable positions can be induced by a shape anisotropy of the free ferromagnetic region wherein each N stable position has a unique resistance value.

Multi-state magnetoresistance random access cell with improved memory storage density

A multi-state magnetoresistive random access memory device having a pinned ferromagnetic region with a magnetic moment vector fixed in a preferred direction in the absence of an applied magnetic field, an non-ferromagnetic spacer layer positioned on the pinned ferromagnetic region, and a free ferromagnetic region with an anisotropy designed to provide a free magnetic moment vector within the free ferromagnetic region with N stable positions, wherein N is a whole number greater than two, positioned on the non-ferromagnetic spacer layer. The number N of stable positions can he induced by a shape anisotropy of the free ferromagnetic region wherein each N stable position has a unique resistance value.

An exemplary system and method of employing DNA hybridization for the detection of bio-agents is disclosed as comprising inter alia a biomolecular rotary motor (); a capture probe DNA fragment () effectively attached to said biomolecular motor (); a target DNA fragment () suitably adapted for hybridization with said capture probe DNA (); a signal probe DNA fragment () suitably adapted for hybridization with said target DNA (); and a fluorescent bead () attached to said signal probe DNA (). Disclosed features and specifications may be variously controlled, adapted or otherwise optionally modified to improve certain device fabrication parameters and/or performance metrics.

Single molecule detection of bio-agents using the F1-ATPase biomolecular motor

Efficient cell lysis in small samples, i.e., samples less than one milliliter, is achieved by exposing the sample to microwave radiation in the frequency range of 18 to 26 GHz. The sample containing cells is supported in a wave-guide cavity, and a microwave source provides microwave radiation to the input port of the wave-guide cavity. A computer controls the frequency and source power level of the microwave radiation produced by the microwave source. The computer also monitors the input power level of the microwave radiation at the input port by means of an input power measuring instrument, the output power level at the output port by means of an output power measuring instrument, and the temperature of the sample by means of a thermocouple. In this way, the computer can control the operating parameters to achieve efficient cell lysis.

System and method for microwave cell lysing of small samples

A self oscillating mixer circuit includes a dual gate FET, an NDR device coupled to a first gate of the FET, and a first bias input circuit adapted to couple a first bias voltage across the NDR device. The first bias voltage controls operation of the NDR device within an NDR region of the V-I characteristic curve of the NDR device so that oscillations occur in the NDR device and the FET. The first bias input circuit is adjustable to adjust the applied first bias voltage so as to control frequency and amplitude of the oscillations. An RF input terminal and a second bias input circuit are coupled to supply a second bias voltage at the other gate terminal, which biases the FET at maximum gain so that RF signals applied to the RF input terminal are mixed with the oscillations.

Self oscillating mixer

A magneto-electronic component includes a first current line ( ) for generating a first magnetic field, a magnetic memory cell ( ), and a second current line ( ) for generating a second magnetic field and substantially perpendicular to the first current line. The magnetic memory cell includes a multi-state memory layer having a structure adjacent to the first current line such that a magnetic flux emanating from the multi-state memory layer is substantially confined to wrap around the first current line. The second current line is located adjacent to a portion of the multi-state memory layer.

Magnetic memory cell having magnetic flux wrapping around a bit line and method of manufacturing thereof

A sparse-carrier device including a crystal structure ( ) formed of a first material and having a crystallographic facet ( ) with a width (w) and a length and quantum dots ( ) formed of a second material and positioned in at least one row on the crystallographic facet ( ). The at least one row of quantum dots ( ) extends along the length of the crystallographic facet ( ) and is at least one quantum dot ( ) wide (w) and a plurality of quantum dots long. The number of quantum dot rows determined by the width (w) of the crystallographic facet ( ). The row of quantum dots ( ) form a building block for circuits based on sparse or single electron devices.

Sparse-carrier devices and method of fabrication

A sparse-carrier device includes a crystal structure with a crystallographic facet having contacts at opposite ends. Quantum dots are formed in first and second rows on the facet approximately one quantum dot wide and a plurality of quantum dots long, the quantum dots in the first row being separated from each other by a first distance smaller than a second distance between the quantum dots in the first row and adjacent quantum dots in a second row. The first distance is small enough to allow carrier tunneling between adjacent quantum dots and the second distance is large enough to substantially prevent tunneling between adjacent quantum dots and small enough to allow Coulombic interaction between adjacent quantum dots. Electrical contacts are formed at opposite ends of the rows to allow tunneling of carriers into and out of quantum dots in the first and second rows.

A symmetric magnetic tunnel device including first and second magnetic tunnel junctions each including a pinned magnetic layer, an insulating tunnel layer and a free magnetic layer stacked in parallel juxtaposition to allow tunneling of electrons through the insulating tunnel layer between the pinned and free magnetic layers. The first and second magnetic tunnel junctions positioned in parallel juxtaposition so as to form a continuous electron path through the first and second magnetic tunnel junctions and to provide a cell signal across the first and second magnetic tunnel junctions greater than a cell signal across each of the first and second magnetic tunnel junctions individually.

Symmetric magnetic tunnel device

A multi-state, multi-layer magnetic memory cell including a first conductor, a first magnetic layer contacting the first conductor, an insulating layer on the first magnetic layer, a second magnetic layer on the insulating layer, a second conductor contacting the second magnetic layer, and a word line adjacent, or in contact with, the cell so as to provide a magnetic field to partially switch magnetic vectors along the length of the first magnetic layer. Information is stored by passing one current through the word line and a second current through the first and second conductors sufficient to switch vectors in the first and second magnetic layers. Sensing is accomplished by passing a read current through a word line sufficient to switch one layer (and not the other) and a sense current through the cell, by way of the first and second conductors, and measuring a resistance across the cell.

Multi-layer magnet tunneling junction memory cells

A method of fabricating 3D semiconductor circuits including providing a conductive layer with doped polysilicon thereon patterned and annealed to form first single grain polysilicon terminals of semiconductor devices. Insulated gate contacts are spaced vertically from the terminals so as to define vertical vias and polysilicon is deposited in the vias to form conduction channels. An upper portion of the polysilicon in the vias is doped to form second terminals for the semiconductor devices, and the polysilicon is annealed to convert it to single grain polysilicon. A second electrically conductive layer is deposited and patterned on the second terminal to define second terminal contacts of the semiconductor devices.

Method of fabricating 3D multilayer semiconductor circuits

A VCO includes a transistor having a plurality of negative differential resistance devices coupled in series to the source terminal of the transistor, with each of the devices having a negative differential resistance operating region. Biasing circuits are coupled to the drain and gate terminals along with operating voltages which set the oscillator to operating in a negative differential resistance region of at least one of the negative differential resistance devices so that oscillations of a selected frequency are produced at an output terminal. The transistor, the plurality of N devices, the DC biasing circuits, and the operating voltages are connected so that the oscillator negative differential resistance operating region is greater than N times as wide as each of the device negative differential operating regions individually.

VCO with multiple negative differential resistance devices

A high efficiency power amplifier includes an integrated circuit with a heterojunction interband tunneling field effect transistor (HITFET) amplifier coupled to receive high frequency (into the GHz) RF signals. The HITFET amplifier is constructed to receive the RF signal with a given frequency at the input terminal and to produce a substantially square wave signal at the given frequency at an output terminal in response to the RF signal applied to the input terminal. The gate of a switching FET connected as a class E amplifier is coupled to the output of the HITFET for receiving the square wave signal and an impedance matching output circuit is coupled to the drain of the switching FET.

High efficiency power amplifier using HITFET driver circuit

A magnetic random access memory (10) has a plurality of stacked memory cells on semiconductor substrate (11), each cell basically having a portion of magnetic material (12), a word line (13), and sense line (14). Upper sense line (22) is electrically coupled to lower sense line (12) via conductor line (23) with ohmic contacts. In order to read and store states in the memory cell, lower and upper word lines (13, 18) are activated, thereby total magnetic field is applied to portion of magnetic material (11). This stacked memory structure allows magnetic random access memory (10) to integrate more memory cells on semiconductor substrate (11).

Magnetic random access memory having stacked memory cells and

A complementary heterojunction semiconductor device (10) has a first resonant interband tunneling transistor (12) coupled to a second resonant interband tunneling transistor (14) through a common output (16). The first transistor (12) has a first gate (18) of a first semiconductor type and a drain (28) coupled to the first gate (18). The first gate (18) is also coupled to the common output (16). The second transistor (14) has a second gate (32) of a second semiconductor type and a source (42) coupled to the second gate (32). The second gate (32) is also coupled to the common output (16). The valence band (60,80,82) of the first semiconductor type has an energy level greater than the conduction band (62,64,84) of the second semiconductor type.

Growing community of inventors

Tempe, AZ, United States of America

Herbert Goronkin