Itt Industries, Inc.

Deutsche Itt Industries Gmbh

Herbert Elmis

Hermannus Schat

Bernd Novotny

Dietmar Ehrhardt

Otmar Kappeler

Adrian Klar

Reiner Backes

Wolfgang Gollinger

Dieter Holzmann

Herbert Alrutz

Heinrich Koehne

Holger Struthoff

Detlev Kunz

Hermann Zibold

Gerhard G Gassmann

Gerhard Gunter

A video signal clamping circuit for adapting the DC level of a composite video signal to the processing range of a digital video signal processing device, includes an isolating capacitor in the analog video signal path and a controlled current source which is connected to a floating isolating-capacitor terminal and charges or discharges the isolating capacitor solely by means of a positive or negative clamping current, with the value and sign of the clamping pulses being digitally controlled by a comparator circuit which compares predetermined reference values of the composite video signal with mode-dependent comparison values.

Video signal clamping circuit

The frequency conversion of an RF signal is performed by the 'third method' using a suitable frequency reversal which makes the frequencies of the picture carrier, the chrominance subcarrier, and at least one sound carrier appear transformed into the baseband, such that the frequencies of the transformed picture carrier and the transformed chrominance subcarrier coincide. Unavoidable differences in the signal paths of the frequency reversal result in a spurious signal which produces a temporally/locally varying moire on the screen. By means of a frequency offset, this spurious signal is transformed into a frequency range which is not found annoying by the observer, so that the moire becomes invisible. This frequency range is preferably the exact center region between two spectral lines of the horizontal frequency of the composite color signal in the baseband.

Frequency conversion of an RF signal transmitted for color-television

A television sound receiving circuit for at least one sound channel contained in an RF signal converts the transmitted or already down-converted television signal as a composite signal to the baseband in a single-sideband demodulator circuit using the 'phasing method', separates the first sound channel, corresponding to a lower sideband, and the second sound channel, corresponding to an upper sideband, and produces first and second sound signals at the desired frequency by subsequent frequency demodulation. Also shown are the interfaces for possible digitization and an advantageous use of the interfaces in which picture and sound signals are digitized together. The data can be combined into a single data stream which can be transferred over a bus system and is separable into the individual components if required.

Television sound receiving circuit for at least one sound channel

A digital synchronization operation circuit synchronizes a pulse train with horizontal synchronizing pulses contained in a received standard television signal which, after being demodulated in the television receiver, is present as the composite color signal and which is fed to an analog-to-digital converter clocked by a clock signal. The digital synchronization separation circuit has an improved phase resolution such that the phase resolution is greater than the resolution provided by the pulse width of clocking signals.

Digital circuit for synchronizing a pulse train

The invention provides a digital circuit for generating a binary signal output when a predetermined frequency ratio, v=f1/f2, of two signals F1 and F2 occurs during a selected measuring period. The circuit is particularly adapted for use in a color television receiver to determine the ratio between the chrominance-subcarrier frequency and the horizontal frequency, which ratio is fixed at the transmitting end, both in the PAL system and the NTSC system.

Digital circuit for providing a binary signal on the occurrence of a

To prevent the separation-level shift occurring in the clamping circuit during the transmitted vertical synchronizing pulses or during prolonged interference pulses, a pulse opening an electronic switch (S) inserted between the clamping circuit and one RC section thereof is generated by means of a coincidence stage (KO), a gate circuit (TS), an inverter (I), and an AND gate (U). The clamping circuit is thus unblocked only during the horizontal synchronizing pulses, so that no shift of the separation level can occur during the vertical synchronizing pulses or during any interference pulses in the composite color signal (F).

Integrated circuit for television receivers comprising a sonic separator

A frequency/phase locked loop for providing signals which are frequency and phase locked to signals at a reference frequency from a reference oscillator which is determinative of the frequency stability includes a frequency-controlled generator of a lower frequency stability. The frequency controlled generator is responsive to control signals for switching between first and second frequencies which are substantially higher than the reference frequency. The second frequency is approximately one to ten percent higher than the first frequency. The frequency divider coupled to the frequency generator provides an output signal at the same frequency as the reference oscillator. A digital phase comparator compares the outputs of the frequency divider with the reference signals. A digital integrating stage coupled to the comparator provides the control signals such that during a first portion of a period of the reference signals the first frequency is selected and during a second portion of the period the second frequency is selected.

Digital frequency/phase locked loop

Division by fractions is accomplished with a counter (Z) presettable to integers and a digitally adjustable delay line (V) following this counter. The fractional parts (b) of the divisor, which are held in decimal point representation (a+0.b) in a divisor register (R), are applied to a first adder (A1) followed by a buffer memory (S), and the integral parts (a) of this divisor are applied to a second adder (A2). The output of the buffer memory (S) is coupled to the set input (Es) of the delay line (V) and to the second input (E2) of the first adder (A1). Thus, at the input of the delay line (V), the number corresponding to the fractional parts (b) is continuously increased by the fractional parts (b) until the overflow output (Ao) of the first adder (A1) provides a signal which is applied to the least significant digit (LB) of the first input (E1) of the second adder (A2). One unit is thus added to the integral parts (a), and the counter (Z) counts one additional digit for one cycle. For arbitrary fractional divisors, the maximum phase-jitter amplitude is equal to the smallest adjustable time delay and, hence, considerably smaller than the clock period (T') of the signal to be divided (F).

Frequency divider presettable to fractional divisors

To adjust time delays in equidistant steps, an inverter chain is provided with an even number of static inverters of identical topology. The output of one of the even-numbered inverters is connected to the signal output via a selector switch. During suitable frequency-measuring periods, an odd number of inverters is connected to form a ring by directly coupling the output of an odd-numbered inverter to the input of the first, and a digital measuring arrangement determines the time delay of the ring-connected portion from the frequency of the ring's self-excited oscillation. The output signal of the measuring arrangement is used to adjust the time delay of the inverter chain.

MOSFET Integrated delay circuit for digital signals and its use in

A circuit for digitally evaluating the magnitude of the phase error between a reference and a locally generated train (sequence) of pulses. The reference train (sequence) may be, for example, the received horizontal sync pulse in a television receiver and the locally generated synchronizable horizontal trigger of the receiver. The reference pulse train (sequence) contains statistical noise and noise pulses and by multiple phase error sampling (digital) and averaging a much more accurate phase error measurement is obtained. Circuits for directly synchronizing the local trigger generator from the measured phase error are also included.

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Denzlingen, Germany

Herbert Elmis