Siemens Aktiengesellschaft

Infineon Technologies Ag

Herbert Eichfeld

Thomas Kuenemund

Christian Paulus

Heinz Mattes

Ralf Klein

Thomas Kunemund

Dirk R&ouml;mer

Markus Waidelich

Dirk Romer

Reiner Lederle

Michael Lohner

The invention relates to an arrangement ( ) and a method for adjusting the slope times of one or more drivers ( ) in such a way that the adjustment is essentially independent of external conditions. The invention also relates to a driver circuit. The arrangement ( ) is provided with a device ( ) for detecting the time history of an output voltage that is output and supplied to a load ( ) by means of the driver/s ( ). The measured time values are converted into an output voltage value in a device ( ) for converting the measured time history of the output voltage. Moreover, a device ( ) for generating a reference voltage value is provided. The device ( ) is connected to a device ( ) for predetermining a desired slope time for the driver/s ( ), whereby the slope time is essentially independent of external conditions. A system pulse can be partitioned into differently long rectangular pulses in the device ( ) in such a way that the user of the arrangement ( ) can select from the group of the rectangular pulses which match certain slope times respectively. The output voltage value and the reference voltage value are compared in a comparing device ( ) that is also connected to the driver/s ( ) in such a way that the driver/s ( ) can be readjusted thereby.

Arrangement and method for adjustment of the slope times for one or more drivers and a driver circuit

A device for reducing the electromagnetic emission in integrated circuits having driver stages reduces the electromagnetic emission of an integrated circuit without requiring an increase in the blocking capacitance in the process. This is achieved by combining driver stages which do not switch simultaneously to form driver groups, and special wiring of a plurality of blocking capacitors.

Device for reducing the electromagnetic emission in integrated circuits with driver stages

The integrated circuit with programmable pad driver involves an integrated circuit (IS1) with at least one pad driver that has a programming unit (PE) and a plurality of sub-drivers (T1 . . . Tm). A specific driver intensity and edge steepness of the pad driver can be set in that a corresponding plurality of sub-drivers connected to a common terminal contact (PAD) at their output side are activated/deactivated dependent on output signals (P1 . . . Pm) of the programming unit.

Integrated circuit with memory programmable pad driver

Arrangement for the separate processing of fuzzy rules of differing

Defuzzification device for a high-resolution fuzzy logic controller

Self-programming circuit

An apparatus for inference formation and defuzzification has an arithmetic unit, a memory/register unit, and a controller, wherein crisp output signals can be formed from weighting factors and dimensional scaling numbers dependent on control signals with a weighting factor being provided for each linguistic value of the output variables, the dimensional numbers characterizing the membership functions of the linguistic values of the output variables. The apparatus exhibits high processing speed and requires only low storage space, particularly given definitions of the crisp output signal of greater than or equal to eight bits.

Apparatus for inference formation and defuzzification in a

Digital logic circuit for implementing fuzzy logic operators

In a fuzzy logic controller, numbers (NI) for linguistic values of the input signal (I1) and first and further parts of input relevance functions (ZL, ZH) of the input signal (I1) can be stored per input signal (I1 . . . I4) in an input memory (I1MEM . . . I4MEM). The numbers for the linguistic values can be fed directly and via incrementing devices (INC1 . . . INC4) to a regulating decoder (RDEC) through a number multiplexer (MUX1a . . . MUX4a), the regulating decoder supplying addresses for a downstream output memory (OMEM). An output signal of the output memory (OMEM) can be fed directly and the first and further parts of the input relevance functions can be fed via relevance function multiplexers (MUX1b . . . MUX4b) to a minimum/maximum circuit (MINMAX). The fuzzy logic controller is distinguished in particular by a very low storage space requirement and is therefore suitable in particular for fuzzy logic controllers with on-chip memories.

Fuzzy logic controller with optimized storage organization

A fuzzy logic controller is composed of a fuzzification circuit (FUZ), a rule decoder (RDEC), a rule evaluation circuit (RA), an inference circuit (INF), a defuzzification circuit (DFUZ) and a sequencer (CTRL). Numbers (NA) for linguistic values of the output variables together with selection signals (SM) for the definition of the input variables affected by the respective rule formed in the rule decoder and are supplied to the rule evaluation circuit in addition to the values (ME) of the affiliation functions for the linguistic values of the input variables. A weighting signal (G) is generated in the rule evaluation circuit for every linguistic value of the output variables. The advantages obtainable are the high processing speed, the low requirement for chip area, the variable rule format and the selection possibility of different operation modes in the rule evaluation circuit, the inference circuit and the defuzzification circuit.

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Munich, Germany

Herbert Eichfeld