Infineon Technologies Ag

Herbert Benzinger

Manfred Pröll

Stephan Schröder

Manfred Proell

Stephan Schroeder

Jörg Kliewer

Martin Schrems

Ralf Schneider

Dietmar Temmler

Georg Erhard Eggers

Wolfram Karcher

Joerg Kliewer

J&uuml;rgen Faul

Catharina Pusch

Peter Beer

Albrecht Kieslich

Manfred Dobler

Norbert Wirth

Frank Richter

Aurel Von Campenhausen

Koen Van Der Zanden

Reidar Stief

Arndt Gruber

Klaus Feldner

Semiconductor memories () have segmented word lines (), which in each case have a main word line () made of a conductive metal and a plurality of interconnect segments () coupled to the main word line (), which are coupled to the respective main word line () in each case via at least one contact hole filling (). If one of the contact hole fillings () is defective or at high resistance then functional errors of the semiconductor memory occur. The interconnect segments () of two respective word lines () can be short-circuited in pairs with the aid of switching units (), whereby a static current (I) that flows via the contact hole fillings () can be used for electrically stressing the contact hole fillings (). Electrical stressing of contact hole fillings of segmented word lines is thus made possible.

Integrated semiconductor memory and method for electrically stressing an integrated semiconductor memory

An integrated semiconductor memory device includes at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense amplifier, where each memory cell includes a selection transistor and a storage capacitor. The storage capacitor of each memory cell includes a first capacitor electrode and a second capacitor electrode, and the selection transistor of each memory cell includes a first source/drain region that is connected by a first contact connection to one bit line of a pair of bit lines corresponding with the memory cell, and a second source/drain region that is conductively connected to the first capacitor electrode of the storage capacitor of the memory cell. The second capacitor electrode of the storage capacitor of each memory cell is connected to the other bit line of the pair of bit lines corresponding with the memory cell.

Integrated semiconductor memory and method for operating a semiconductor memory

An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third controllable switch and to a second voltage potential via a respective second controllable switch. In order to test whether one of the word lines is connected to the first voltage potential via its respective first and third controllable switches, the one of the word lines is connected to a comparator circuit via the respective second controllable switch and a driver line. After the respective first and third controllable switches have been controlled into the on state, in a test operating state of the integrated semiconductor memory, the respective second controllable switch is controlled into the on state and a potential state on the word line is evaluated by the comparator circuit. The result of the evaluation is fed to an external data terminal by an evaluation signal.

Integrated semiconduct memory with test circuit

A semiconductor memory and a method for operating the latter in order are provided, at least in testwise fashion, to deactivate a word line segment () of a segmented word line not via a first line () otherwise used for deactivation, but rather via a second line () via that the word line segment () is otherwise activated. The second line () can optionally be biased with a second potential (Vpp) provided for activation or with a third potential (Vgnd). If the third potential (Vgnd) is used for at least temporarily deactivating the word line segment (), the word line segment can be driven via a switching element (), which couples the word line segment to the second line (), without the complementary switching element () of the driver segment () having to be used for deactivation. It can thereby be ascertained which of two switching elements () of the driver segment is defective and whether or not the semiconductor memory will function in a manner free of errors after permanent replacement of the word line on account of a floating potential of the tested word line segment ().

Integrated semiconductor memory and method for operating an integrated semiconductor memory

A semiconductor memory and a test method for testing whether word line segments () are floating after an activation operation or a deactivation operation is disclosed. For this purpose, the charge-reversal current (I) that occurs in the event of a word line segment () being subjected to charge reversal or a charge quantity (Q) which is fed to the word line () or conducted away from the word line segment () as a result of this is measured. If, upon activation or deactivation of a word line segment (), the measured charge-reversal current (I) or the corresponding charge quantity (Q) is less than a lower limit value, it is ascertained that the relevant word line segment () has a defective contact terminal. In this way, high-impedance or defective contact hole fillings can thereby be identified and the associated word line segments () can be replaced by redundant word lines.

Integrated semiconductor memory comprising at least one word line and method

An integrated semiconductor memory includes at least one word line and a number of memory cells. Each memory cell has a selection transistor coupled to the word line. A word line driver is coupled to the word line. The word line driver provides a first electrical potential or a second electrical potential to the word line such that the word line is activated by the first electrical potential and is deactivated by the second electrical potential. A passive component (e.g., a diode or a resistor) is coupled between the word line and the second electrical potential such that the word line is coupled to the second electrical potential in a high-resistance fashion through the passive component. The passive component is transmissive for a leakage current between the word line and the contact connection.

Integrated semiconductor memory comprising at least one word line and comprising a multiplicity of memory cells

A semiconductor memory includes storage cells () that have storage capacitors and transistors with an electrode, which is electrically biasable with two different electrical potentials (VV) in order to open and close the transistor. The electrode potential (V) intended for the off state of the transistor is a temperature-dependent potential, the value of which is controlled temperature-dependently by the semiconductor memory () so that the second electrical potential (V) becomes more different from the first electrical potential (V) as the temperature (T) increases.

Semiconductor memory and method for operating a semiconductor memory

An integrated semiconductor memory device includes a memory cell array (B) with a first bit line and a second bit line (BL, /BL), a controllable resistor (SW) and a control unit () configured to control the controllable resistor. In a first operating state of the integrated semiconductor memory device, the first and second bit lines are connected to one another via a first controllable switch (ET) and also via the controllable resistor (SW) which has been set to a low resistance, to a connection (A) that applies a mid-voltage (V), where the voltage level of the mid-voltage is in the form of an arithmetic mean between a first and second voltage potential (VBLH, VBLL). By virtue of the control unit briefly setting the controllable resistor to a very low resistance in the first operating state of the integrated semiconductor memory device, the period of time required for the first and second bit lines require to assume the mid-voltage (V) is shortened. The influence of capacitive coupling influences, which slow down the charging of the first and second bit lines to the mid-voltage, is significantly reduced as a result.

Integrated semiconductor memory device and method for operating an integrated semiconductor memory device

A circuit arrangement for setting a voltage supply for a read/write amplifier of an integrated memory has a first voltage generator circuit for generating a supply voltage for application to the read/write amplifier during an assessment and amplification operation and a second voltage generator circuit for generating a precharge voltage for precharging bit lines of the memory which are connected to the read/write amplifier. A temperature detector circuit, which is connected to the first voltage generator circuit, is used to detect a temperature of the memory and interacts with the first voltage generator circuit to set the supply voltage applied to the read/write amplifier in a manner depending on a temperature of the memory.

Circuit arrangement and method for setting a voltage supply for a read/write amplifier of an integrated memory

An integrated memory can include a memory cell array, which has word lines for the selection of memory cells, bit lines for reading out or writing data signals of the memory cells, and a sense amplifier connected to bit lines of a bit line pair at one end of the bit line pair. In an activated state during a memory access, at least one activatable isolation circuit which is switched into one of the bit line pairs can isolate a part of the bit line pair, which is more remote from the sense amplifier from the sense amplifier. As a result, the effective capacitance of the bit lines can be significantly reduced during the memory access.

Integrated memory

A DRAM cell configuration is described in which a memory cell in each case has a storage capacitor and a read-out transistor. For connecting to the read-out transistor, a buried strap contact is produced by outdiffusion of dopants from the electrode of the storage capacitor. The buried strap contact is superposed by the implantations of the source/drain region of the read-out transistor, so that the implantations of the source/drain region form the boundary of the space charge zone of a p/n junction of the memory cell.

DRAM cell configuration and method for fabricating the DRAM cell configuration

A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting the trench capacitor to the transistor with a self-aligned connection. The transistor at least partly covers the trench capacitor. The trench capacitor is filled with a conductive trench filling and an insulating covering layer is situated on the conductive trench filling. An epitaxial layer is situated above the insulating covering layer. The transistor is formed in the epitaxial layer. The self-aligned connection is formed in a contact trench and includes an insulation collar in which a conductive material is introduced. A conductive cap is formed on the conductive material.

Memory with trench capacitor and selection transistor and method for fabricating it

An integrated memory has a memory cell array containing word lines and bit lines. The bit lines, for reading out a data signal, can in each case be connected to a sense amplifier via a controllable switching device. Furthermore, a control circuit is contained, having an output, which is connected to a control input of the respective switching device, and having an input, which is connected to a terminal for a test mode signal. The control circuit is configured in such a way that, within an access cycle, the respective switching device can be switched into a non-conducting state on account of an active state of the test mode signal. In the integrated memory, it is possible to measure the leakage behavior of a bit line during the read-out of a data signal.

Integrated memory and method for testing an integrated memory

A method for producing a semiconductor device having a first region with storage capacitors and a second region with at least one well surrounded by an insulation. The method creates both the storage capacitors and the insulation by forming trenches in the first region and at least one trench in the second region, and the trenches have a depth of at least 2 &mgr;m. The trenches in the first region are treated to provide first and second electrodes separated by a dielectric to form the capacitors and each trench in the second region provides an insulation which surrounds any wells in the second region.

Method for producing an insulation

A circuit configuration and a method for the synchronization of signals include transmitting signals in parallel through data lines and buffer-storing the signals in a synchronizing unit. A clock signal is determined from the signals of a data line and is used for synchronizing the outputting of the signals. The signals are output in the order in which the signals were read. The signals are likewise output through a plurality of data lines, the signals being output temporally synchronously. Propagation time differences are compensated due to the buffer-storage. Moreover, the clock signal is determined from the signals themselves. Consequently, the use of an additional clock signal is not necessary.

Growing community of inventors

Munich, Germany

Herbert Benzinger