Micronas Gmbh

Deutsche Itt Industries Gmbh

Micronas Intermetall Gmbh

Herbert Alrutz

Andreas Menkhoff

Matthias Vierthaler

Miodrag Temerinac

Herbert Elmis

Heinrich Koehne

Dejan Lazich

Steffen Schober

Hermann Zibold

Dieter Lücking

William Butera

A method for generating random numbers in which oscillating digital output signals of unequal or equal periodicity are generated by at least two ring oscillators, an external parity signal representing a logical state being generated when an odd number of the output signals take on a specified logical state, the external parity signal being fed back to an external parity input of each of the respective ring oscillators. Also, a random number generator having at least two ring oscillators made up of independently freewnning inverter chains with feedback having an odd number of series-connected inverters that generate oscillating digital output signals of unequal or equal periodicity, and having first panty signal generating mechanisms that generate an external parity signal representing a logical state when an odd number of the output signals take on a specified logical state.

System and method for generating random numbers using parity feedback

A digital filter combination for interpolating primary sample values of a sampled signal using an mth-order discrete-time filter and a kth-order continuous time interpolation filter, with m&#x2267;3 and k&#x2267;2, wherein the discrete-time filter forms n secondary sample values from at least m+1 primary sample values at equal time intervals, with n&#x2267;m, and the continuous-time interpolation filter forms from at least part of the n secondary sample values an interpolated value whose temporal position with respect to that of the primary sample values is predeterminable by a normalized interpolating instant dp=t/T, where tis the absolute interpolating instant, and T is the period of the primary sampling rate.

Digital filter combination for interpolation

The invention relates to a method and a device for converting a digital, pulse-coded signal (PCM) to a pulse-width-modulated signal (PWM), wherein the digital signal PCM, f(t) is multiplied by at least one derivative (f'(t), f&#x2033;(t), . . . , f(t)) of the signal (f(t)). The invention also relates to a technique for converting a digital pulse-coded signal (PCM) to a pulse-width-modulated signal (PWM), wherein to obtain a sampling rate sufficient for the pulse-width-modulated signal an oversampling of the digital signal is implemented with a first oversampling factor before the conversion and an second oversampling factor after the conversion, such that the product of the oversampling factors before and after conversion of the digital signal to the pulse-width-modulated signal corresponds at least to the value of the required oversampling factor.

PCM-to-PWM converter

A filter combination for sampling rate conversion is disclosed comprising a series combination of: an input low-pass filter (1) whose attenuation characteristic (tp1) has at least one first attenuation value (a1) in the vicinity of one-half and 1.5 times the frequency of a digitization clock (f1); a time-invariant interpolation filter (2) for increasing the number of samples from that of the first data sequence (d1) by an integral factor whose attenuation characteristic (tp2) has at least one second attenuation value (a2) in the vicinity of the frequency of the digitization clock (f1) and essentially at least one third attenuation value (a3) in the region between one-half and 1.5 times the frequency of the digitization clock; and a time-varying interpolation filter (3) for interpolating a data sequence (d5) provided at the output of the time-invariant interpolation filter (2), the attenuation characteristic (tp3) of the time-varying interpolation filter (3) having at least one fourth attenuation value (a4) in the vicinity of twice the frequency of the digitization clock (f1).

Filter combination for sampling rate conversion

A video signal clamping circuit for adapting the DC level of a composite video signal to the processing range of a digital video signal processing device, includes an isolating capacitor in the analog video signal path and a controlled current source which is connected to a floating isolating-capacitor terminal and charges or discharges the isolating capacitor solely by means of a positive or negative clamping current, with the value and sign of the clamping pulses being digitally controlled by a comparator circuit which compares predetermined reference values of the composite video signal with mode-dependent comparison values.

Video signal clamping circuit

One-dimensional or multi-dimensional digitized signals are transformed into one-dimensional or multi-dimensional output signals by clock-rate conversion of subband signals. To synthesize the output signal at least one continuous subset of primary subband signals is used. The subset includes the subband signal with the lowest frequency range. During reproduction of images which are horizontally and vertically scanned and digitized, absolute and relative format changes can be implemented by the clock-rate conversion.

Growing community of inventors

Freiburg, Germany

Herbert Alrutz