Broadcom Corporation

Heratch Avakian

Shane Patrick Lansing

The present invention provides methods for performing payload header suppression (PHS), expansion, and verification in hardware. A PHS verify circuit reads a data packet until it reaches the location where the first byte must be compared to PHS rule verify bytes. Next, all the relevant bytes in the payload header are compared to the PHS vile verify bytes obtained from a payload header suppression rule mask. Upon completion of the compare, a flag is generated to a PHS suppress circuit indicating that verification has passed or failed. For payload headers passing the verification process, the payload header suppress circuit examines the payload header suppression mask to identify one or more bits in the payload header for which an associated byte string is to be suppressed. Next, the associated byte string for each of the identified bits are suppressed to generate a suppressed packet payload header. Finally, a payload header suppression index is added to the suppressed packet payload header. The data packet, including the suppressed packet header and suppression index are then transmitted. Once received, a payload header suppress circuit on the receiver end examines the payload header suppression index to determine if the payload header has been suppressed. For each suppressed payload header, each bit in the payload header is compared to a payload header suppression mask to determine if the bit has been suppressed. Next, for each suppressed bit, a byte string is retrieved from a payload header suppression rule and inserted into the suppressed payload header.

Apparatus and method for hardware payload header suppression, expansion, and verification

The present invention provides methods for performing payload header suppression (PHS), expansion, and verification in hardware. A PHS verify circuit reads a data packet until it reaches the location where the first byte must be compared to PHS rule verify bytes. Next, all the relevant bytes in the payload header are compared to the PHS rule verify bytes obtained from a payload header suppression rule mask. Upon completion of the compare, a flag is generated to a PHS suppress circuit indicating that verification has passed or failed. For payload headers passing the verification process, the payload header suppress circuit examines the payload header suppression mask to identify one or more bits in the payload header for which an associated byte string is to be suppressed. Next, the associated byte string for each of the identified bits are suppressed to generate a suppressed packet payload header. Finally, a payload header suppression index is added to the suppressed packet payload header. The data packet, including the suppressed packet header and suppression index are then transmitted. Once received, a payload header suppress circuit on the receiver end examines the payload header suppression index to determine if the payload header has been suppressed. For each suppressed payload header, each bit in the payload header is compared to a payload header suppression mask to determine if the bit has been suppressed. Next, for each suppressed bit, a byte string is retrieved from a payload header suppression rule and inserted into the suppressed payload header.

System and method for hardware payload header suppression, expansion, and verification in a wireless network

A media access controller (MAC) is configured with a header creator circuit. The header creator circuit is configured with logic for receiving a data packet and determining whether the received data packet has an existing packet header prepended thereto. The header creator circuit is further configured to determine if the length of the received data packet includes a cyclic redundancy code. Still further, the header creator circuit is configured to determine a packet header length field value for the received data packet. If the header creator circuit determines that a cyclic redundancy code needs to be included with the received data packet, then the header creator circuit is able to generate a CRC flag. If the data packet needs to be encrypted, then the header creator circuit will generate an encryption flag if it is determined that the received data packet should be encrypted. Finally, the header creator circuit generates a packet header having a plurality of fields.

Apparatus and method for hardware creation of a header

The present invention provides apparatus and methods for performing payload header suppression (PHS), expansion, and verification in hardware. A PHS verify circuit reads a data packet until it reaches the location where the first byte must be compared to PHS rule verify bytes. Next, all the relevant bytes in the payload header are compared to the PHS rule verify bytes obtained from a payload header suppression rule mask. Upon completion of the compare, a flag is generated to a PHS suppress circuit indicating that verification has passed or failed. For payload headers passing the verification process, one or more bits are suppressed in the payload header and a the payload header suppressed and a payload header suppression index is added to the suppressed packet payload header. Following transmission, the suppression indexed is used to identify the bits to be reinserted into the suppressed payload header.

Apparatus and methods for hardware payload header suppression, expansion, and verification in a DOCSIS network

A media access controller (MAC) is configured with a DOCSIS Header creator circuit. The DOCSIS header creator circuit is configured with logic for receiving a data packet and determining whether the received data packet has an existing packet header prepended thereto. The DOCSIS header creator circuit is further configured to determine if the length of the received data packet includes a cyclic redundancy code. Still further, the DOCSIS header creator circuit is configured to determine a packet header length field value for the received data packet. If the DOCSIS header creator circuit determines that a cyclic redundancy code needs to be included in with the received data packet, then the DOCSIS header creator circuit is able to generate a CRC flag. If the data packet needs to be encrypted, then the DOCSIS header creator circuit will generate an encryption flag if it is determined that the received data packet should be encrypted. Finally, the DOCSIS header creator circuit generates a DOCSIS packet header having a plurality of fields.

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Glendale, CA, United States of America

Heratch Avakian