Intel Corporation

Heonwook Kim

Aliasgar S Madraswala

Kristopher H Gaewsky

Purval Shyam Sule

Sriram Balasubrahmanyam

Varsha Regulapati

Naga Kiranmayee Upadhyayula

Tanya Wanchoo

Manjiri M Katmore

Siddhanth Munukutla

Jong Tai Park

Embodiments of the present disclosure are directed towards techniques and configurations for a memory apparatus configured with an erase command comprising a sequence of segments. In one embodiment, the memory apparatus is configured to generate an erase command in response to a request provided by a host to erase at least a portion of data stored in a memory device. The erase command comprises a sequence of erase segments that provide an erase voltage for erasing the portion of data stored in the memory apparatus. The memory apparatus is configured to grant access to the memory apparatus for servicing the memory access requests initiated by the host, during a time period between at least two adjacent erase segments in the sequence. Other embodiments may be described and/or claimed.

Method and apparatus for performing an erase operation comprising a sequence of micro-pulses in a memory device

In connection with data pin timing calibration with a strobe signal, examples provide for determination of pass/fail status of a pin from multiple pass/fail results in a single operation. Determination of pass/fail results for multiple pins based on multiple applied trim offsets can be made in parallel. Accordingly, a time to determine pass/fail results from multiple trim values for a pin can be reduced, which can enable faster power-up of NAND flash devices.

Techniques for providing signal calibration data

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San Jose, CA, United States of America

Heonwook Kim