Silicon Image Gmbh

Samsung Electronics Co., Ltd.

Heon Kim

Chinsong Sul

Gijung Ahn

Jin-Young Park

In some embodiments, a chip includes first and second scan chain segments each including registers and multiplexers to provide to the registers scan input signals during scan input periods and captured output signals during a capture periods. The chip also includes circuitry to provide first and second test clock signals to the registers of the first and second scan chain segments, respectively, wherein the second test clock signal is provided by a different signal path in the circuitry during the scan input periods than during the capture periods, and during the scan input periods the second test clock signal is skewed with respect to the first test clock signal. Other embodiments are described and claimed.

Circuitry to prevent peak power problems during scan shift

In some embodiments, an apparatus includes conductors, and a transmitter including transmitter test circuitry to embed test properties in test pattern signals, and transmit the test pattern signals to the conductors. In some embodiments, an apparatus includes conductors to carry test pattern signals with embedded test properties, and receiver test circuitry to receive the test pattern signals and extract the test properties and determine whether the extracted test properties match expected test properties. Other embodiments are described and claimed.

Interface test circuitry and methods

A built-in self test (BIST) circuit and method is provided for testing semiconductor memory. A linear feedback shift register (LFSR) is used for addressing the memory locations to be tested. Test data is derived at least partially from the address data generated from the linear feedback shift register.

Growing community of inventors

San Jose, CA, United States of America

Heon Kim