Samsung Electronics Co., Ltd.

Heon-jong Shin

Sung-Min Kim

Hwi-Chan Jun

Jae-ran Jang

Sunhom Steve Paak

Dong-Ho Cha

In-chan Hwang

Shigenobu Maeda

Cheol Kyu Kim

Seung-hwan Lee

Hee-Sung Kang

Jong-Ryeol Yoo

Seong-Hoon Jeong

Hyun-jung Lee

Jeong-Hoon Ahn

Kyung-Seok Oh

Abraham Yoo

Dong-kyun Nam

Hyung-tae Ji

Young-ki Lee

Ji-woon Rim

Sung-rey Wi

Sung-Hoon Kim

Soo-cheol Lee

Hyun-Min Choi

Sung-hoon Lee

Jong-hyon Ahn

Kyung-Tae Lee

Hwa-Sook Shin

Young-Ki Lee

Hyae-Ryoung Lee

Sang-don Yi

Young-woo Cho

Hyun-min Choi

Young-hwan Oh

Dae-Hee Weon

Yu-Sun Lee

Kyoung-mok Son

Young-pill Kim

Moo-jin Jung

Jae-Cheol Yoo

Son-jong Wang

WangXiao Quan

Quan WangXiao

Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.

Semiconductor devices and methods of forming the same

An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gate line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

Integrated circuit device and method of fabricating the same

An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.

Semiconductor devices having lower and upper fins and method for fabricating the same

Methods of forming a semiconductor device are provided. The methods may include forming a gate structure on a substrate, forming a first sacrificial pattern and a second sacrificial pattern on opposing sides of the gate structure respectively and partially replacing the first sacrificial pattern with a first insulating pattern such that a portion of the first sacrificial pattern remains in the first insulating pattern and replacing the second sacrificial pattern with a second insulating pattern. The methods may also include replacing at least some of the portion of the first sacrificial pattern that remains in the first insulating pattern with a conductive pattern.

Methods for fabricating semiconductor devices

In a semiconductor device, a first gate structure having a first end portion is formed on a substrate. A second gate structure is formed on the substrate, and has a second end portion opposite to the first end portion of the first gate structure in a diagonal direction. A cross-coupling pattern is formed between the first and second gate structure, and electrically connects the first and second gate structures to each other. A first contact plug directly contacts an upper portion of the first end portion of the first gate structure and a first upper sidewall of the cross-coupling pattern. A second contact plug directly contacts an upper portion of the second end portion of the second gate structure and a second upper sidewall of the cross-coupling pattern. In the semiconductor device, a parasitic capacitance due to the cross-coupling structure may decrease.

Semiconductor device having a gate cutting region and a cross-coupling pattern between gate structures

A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and gate dummies not to overlap each other, the area of active dummy on which a strain layer dummy will be formed can be secured, thereby reducing the loading effect.

Semiconductor device structure with strain layer

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Yongin-si, South Korea

Heon-jong Shin