Samsung Electronics Co., Ltd.

Heon Gwon Lee

Dae-Jeong Kim

Kwang-woo Lee

Woo Young Yang

Dae Jeong Kim

Kwang Woo Lee

In Ho Cho

Kab Yong Kim

Inho Cho

Hoon-Chang Yang

Kabyong Kim

A storage device, a storage system comprising the same, and operating methods of the storage device are provided. The storage device includes a first nonvolatile memory cell array which includes a plurality of cell strings arranged in a direction perpendicular to a substrate, and stores first data at a first address, a second nonvolatile memory cell array which stores second data selected from the first data at a second address, in accordance with an access pattern to the first data, and a memory controller which manages a first mapping table indicating that the second data is stored at the second address of the second nonvolatile memory cell array, and a second mapping table indicating that the first data as original data of the second data is stored at the first address.

Storage device, storage system comprising the same, and operating methods of the storage device

A method is provided for refreshing a volatile memory. The method includes storing address information about a weak cell row address that is to be refreshed according to a weak cell refresh period that is shorter than a refresh period, performing a counting operation for generating a refresh row address, comparing the refresh row address with the address information, refreshing the weak cell row address when a result of the comparison shows that the refresh row address and the weak cell row address of the address information coincide with each other, changing the weak cell row address by changing a pointer of the address information, and refreshing the changed weak cell row address according to the weak cell refresh period.

Method of refreshing volatile memory device

A semiconductor memory device includes: a normal memory cell block including a first plurality of memory cells; a redundancy memory cell block including a second plurality of memory cells and configured for use in replacing memory cells of the normal memory cell block; a weak cell information storage configured to store information regarding weak memory cells in the normal and redundancy memory cell blocks; and a refresh control circuit configured to control a refresh rate of memory cells in the normal and redundancy memory cell blocks based on the information regarding weak memory cells in the weak cell information storage. The weak memory cells in the normal and redundancy memory cell blocks are refreshed at least once more than other memory cells in the normal and redundancy memory cell blocks during a refresh cycle.

Semiconductor memory device and refresh method thereof

A refresh leveraging driving method is provided which includes deciding a unit of word lines to be driven at a refresh leveraging operation to be the same as a redundancy repair row unit setting a lower row address of an input refresh leveraging address corresponding to the decided refresh leveraging row driving unit to a don't care state; and internally generating the don't care lower row address of the refresh leveraging address to drive word lines according to a combined refresh leveraging address.

Semiconductor memory device and refresh leveraging driving method thereof

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Hwaseong-si, South Korea

Heon Gwon Lee