Texas Instruments Corporation

Henry Yao

Jayawardan Janardhanan

Sinjeet Parekh

Vivek G Gupta

Raghu Ganesan

Christopher Andrew Schell

Eric Paul Lindgren

Manikantan Jayaraman

Anindita Borah

A video transfer circuit includes: a first communication interface; a second communication interface; and a digital timing generator having an input, an output, and a video timing signal interface. The input is coupled to the first communication interface. The video timing signal interface is coupled to the second communication interface. The digital timing generator is configured to: provide a first video timing signal to the second communication interface via the video timing signal interface responsive to a first mode selection; and receive a second video timing signal from the second communication interface via the video timing signal interface responsive to a second mode selection.

Video transfer circuit with multi-chip synchronization circuitry

A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.

Time-to-digital converter circuit

A circuit includes a time-to-digital converter (TDC) to produce an output signal that is a function of a time difference between a first input clock to the TDC and a second input clock to the TDC. A first delay line is also included to add a time delay to a third clock to produce the first input clock. A pseudo random binary sequence generator generates a pseudo random binary bit sequence to be used to vary the amount of time delay added by the first delay line to the third clock.

Wobble reduction in an integer mode digital phase locked loop

A phase-locked loop circuit includes a first time-to-digital converter (TDC) to receive an input reference signal, a digital-controlled oscillator (DCO), and a first divider coupled to an output of the DCO. The first divider divides down a frequency of an output from the DCO. A second divider divides down a frequency of an output form the first divider to provide a second divider output to an input of the first TDC. The first TDC generates an output digital value encoding a time difference between corresponding edges of the input reference signal and the second divider output. A second TDC receives the input reference signal. An averager circuit generates a digital output that is indicative of an average of an output from the second TDC. A subtractor circuit subtracts the digital output from the average and the output digital value from the first TDC.

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Henry Yao