Microsoft Technology Licensing, LLC

Northrop Grumman Systems Corporation

Henry Y Luo

Donald Lynn Miller

Ofer Naaman

Quentin P Herr

Randall M Burnett

One example includes a memory cell system. The memory cell system includes a quantizing loop configured to conduct a quantizing current in a first direction corresponding to storage of a first state of a stored memory state of the memory cell system and to conduct the quantizing current in a second direction opposite the first direction corresponding to storage of a second state of the stored memory state of the memory cell system. The memory cell system also includes a bias element arranged in the quantizing loop and which is configured to provide a substantially constant flux bias of the quantizing loop in each of the first and second states of the stored memory state.

Quantizing loop memory cell system

One example includes a memory cell system that includes a quantizing loop that conducts a quantizing current in a first direction corresponding to a first stored memory state and to conduct the quantizing current in a second direction corresponding to a second stored memory state. The system also includes a bias element configured to provide a substantially constant flux bias of the quantizing loop in each of the first and second states of the stored memory state. The stored memory state can be read from the memory cell system in response to the substantially constant flux bias and a read current that is provided to the memory cell system. The system further includes a tunable energy element that is responsive to a write current that is provided to the memory cell system to change the state of the stored memory state between the first state and the second state.

Superconducting integrated circuits with clock signals distributed via an inductive coupling and related methods are provided. A method includes providing a D flip-flop having a clock terminal coupled to receive clock pulses from a clock line, a data input terminal, and a data output terminal. The D flip-flop may further include a first Josephson junction (JJ) coupled between a first terminal and a second terminal. The D flip-flop may further include a superconducting quantum interference device (SQUID) coupled between a third terminal and a fourth terminal, where an inductive loop, formed between the first JJ and the SQUID, is configured to in response to receiving a first clock pulse, store a fluxon when a state of the input data signal is high, and is configured to in response to receiving a second clock pulse to annihilate the stored fluxon when a state of the input data signal is low.

Superconducting integrated circuits with clock signals distributed via inductive coupling

A memory system including an array of memory cells may include a set of word-lines, and a set of return word-lines coupled to the memory cells in the array of memory cells. The memory system may further include a set of bit-lines coupled to the memory cells. Each of the memory cells may include a memory storage element including a readout superconducting quantum interference device (SQUID), and a magnetic Josephson Junction (MJJ), and where the memory storage element may further include a differential transformer coupled in series with the MJJ such that in response to a bit-line current applied to at least one of the set of the bit-lines and a word-line current applied to at least one of the set of word-lines, the differential transformer is configured to induce a flux in the at least one readout SQUID.

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Henry Y Luo