Altera Corporation

Cypress Semiconductor Corporation

Henry Y Lui

Ramanand Venkata

Rakesh H Patel

Chong H Lee

Arch Zaliznyak

Wai-Bor Leung

Surinder Singh

Malik Kabani

Martin Langhammer

David Lewis

John E Turner

Volker Mauer

Keone Streicher

Hyun Mo Yi

Vinson Chan

Victor Maruri

Yi-Wen Lin

Suleyman Sirri Demirsoy

John D Lam

Edward Aung

Paul Butler

Tim Tri Hoang

Tony K Ngai

Sergey Yuryevich Shumarayev

David Wolk Mendel

Thungoc M Tran

Boon Jin Ang

William W Bereza

Kok Heng Choe

Sammy S Cheung

Thow Pang Chong

Andrew J Bellis

Sun Woo Baek

An integrated circuit device may include processing circuits that can be dynamically reconfigured to perform different tasks each of which utilizes different system clock resources. The device may include clock selection circuitry that can selectively route desired clock signals to corresponding processing circuits. The clock signal provided to each processing circuit may be selected based on a current configuration of that processing circuit. Client processing circuits in a network switch may be coupled to interchangeable client networks. The client processing circuits may be dynamically reconfigured based on characteristics of the client networks that are currently coupled to the network switch. By dynamically selecting which clock resources are provided to the processing circuits, clock resources such as global clock signals that are relatively scarce may be reserved for processing circuits that can only function with the relatively scarce clock resources. Arranged in this way, clock resource utilization may be continuously optimized.

Integrated circuits with clock selection circuitry

A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.

Techniques for aligning and reducing skew in serial data signals

One embodiment relates an apparatus which includes a plurality of local synchronous divider circuits, each local synchronous divider circuit being configured to receive a serial clock signal and a reset signal and generate a local clock signal. The apparatus further includes a clock distribution network configured to distribute the serial clock signal to the plurality of local synchronous divider circuits and a signal distribution network configured to distribute the reset signal to the plurality of local synchronous divider circuits. Another embodiment relates to a method of distributing a serial clock signal and a reset signal to a plurality of local synchronous divider circuits and generating a local clock signal at each of the plurality of local synchronous divider circuits. Other embodiments, aspects, and features are also disclosed.

Apparatus and methods for low-skew channel bonding

One embodiment relates to an integrated circuit having a plurality of four-channel serial interface modules. Each of the plurality of four-channel serial interface modules includes a first physical medium attachment (PMA) channel circuit, a second PMA channel circuit adjacent to the first PMA channel circuit, a third PMA channel circuit adjacent to the second PMA channel circuit, a fourth PMA channel circuit adjacent to the third PMA channel circuit, and at least one phase-locked loop (PLL) circuit which is programmably coupled to each of the first, second, third and fourth PMA channel circuits. Other embodiments and features are also disclosed.

Heterogeneous high-speed serial interface system with phase-locked loop architecture and clock distribution system

Digital signal processing ('DSP') circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response ('FIR'), digital filters.

Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry

A method for determining clock uncertainties is provided. The method includes identifying clock transfer types between registers from an integrated circuit design and identifying contributors to the clock uncertainties for each of the clock transfers. The jitter associated with each identified contributor is calculated for both set-up time and hold time. This calculated jitter is incorporated into a slack calculation to determine whether timing constraints are met for a circuit design.

Method and apparatus for determining clock uncertainties

Multiplier-accumulator circuitry includes circuitry for forming a plurality of partial products of multiplier and multiplicand inputs, carry-save adder circuitry for adding together the partial products and another input to produce intermediate sum and carry outputs, final adder circuitry for adding together the intermediate sum and carry outputs to produce a final output, and feedback circuitry for applying the final output (typically after some delay, e.g., due to registration of the final output) to the carry-save adder circuitry as said another input. The above circuitry may be implemented in so-called 'hard IP' (intellectual property) of a field-programmable gate array ('FPGA') integrated circuit device. If desired, any overflow from the accumulation performed by the above circuitry may be accumulated in &#x201c;soft&#x201d; accumulator-overflow circuitry that is implemented in the general-purpose programmable logic of the FPGA.

Multiplier-accumulator circuitry and methods

An integrated circuit includes a local clock network that is operable to provide a first clock signal and an interface circuit that is coupled to receive the first clock signal from the local clock network. The interface circuit is operable to generate a second clock signal based on the first clock signal. A clock line is coupled to the interface circuit. The clock line has a fixed length. The second clock signal is provided to a multiplexer circuit through the clock line. The multiplexer circuit provides a third clock signal based on the second clock signal. Another clock network is coupled to receive the third clock signal from the multiplexer circuit.

Techniques for providing clock signals in clock networks

Disclosed are apparatus and methods for providing a serial interface with shared datapaths. The apparatus and methods share or re-use components from multiple lower-speed datapaths so as to efficiently provide a higher-speed datapath. In one embodiment, physical coding sublayer circuitry of the lower-speed datapaths is also used by the higher-speed datapath. In another embodiment, physical media access circuitry of the lower-speed data paths is also used by the higher-speed datapath. Other embodiments, aspects and features are also disclosed.

Apparatus and methods for serial interfaces with shared datapaths

A programmable integrated circuit device includes a plurality of specialized processing blocks. Each specialized processing block may be small enough to occupy a single row of logic blocks. The specialized processing blocks may be located adjacent one another in different logic block rows, forming a column of adjacent specialized processing blocks. Each specialized processing block includes one or more multipliers based on carry-save adders whose outputs are combined using compressors. Chain-in and chain-out connections to the compressors allow adjacent specialized processing blocks to be cascaded to form arbitrarily large multipliers. Each specialized processing block also includes a carry-propagate adder, and the carry-propagate added in the final specialized processing block of the chain provides the final result. The size of the multiplication that may be performed is limited only by the number of specialized processing blocks in the programmable integrated circuit device.

DSP block for implementing large multiplier on a programmable integrated circuit device

A programmable logic device ('PLD') is augmented with programmable clock data recover ('CDR') circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (&#x201c;LVDS&#x201d;). The circuitry may be part of a larger system.

Clock data recovery circuitry associated with programmable logic device circuitry

A charge pump circuit includes switch circuit modules and current modules. The number of switch circuit modules that are coupled to receive current from one of the current modules is variable. The output current of the charge pump circuit increases as more of the switch circuit modules are coupled to receive current from the current modules. The net on-resistance of the switch circuit modules decreases as more of the switch circuit modules are coupled to receive current from the current modules. Charge coupling caused by the net parasitic gate-to-drain capacitance of switching transistors in the switch circuit modules is reduced at smaller output current settings of the charge pump circuit.

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San Jose, CA, United States of America

Henry Y Lui