National Semiconductor Corporation

Philips Electronics North America Corporation

North American Philips Corp., Signetics Div.

Henry Wei-Ming Chung

Kevin Carl Brown

Tsui Y Yao

A method of forming interconnecting layers in a semiconductor device whereby even if a via is misaligned with a metal line, a portion of the via not enclosed and capped by the metal is enclosed and capped by an etch stop spacer. The foundation layer includes a dielectric layer having a trench formed therein, the trench being filled with a plug material. The foundation layer further includes a barrier layer formed atop the dielectric layer. A metal layer is formed on the surface of the boundary layer, and a protection layer is formed on the surface of the metal layer. The protection layer and the metal layer are patterned to define a line of composite protection/metal on the surface of the boundary layer. An etch stop layer is formed which substantially conforms to the shape of the composite protection/metal line, including etch stop spacers conforming to the sidewall portions of the line. Selected portions of the etch stop layer are removed to expose the protection surface of the composite protection/metal line and portions of the boundary layer, while leaving the etch stop spacers. Portions of the boundary layer between the etch stop spacers are removed. A layer of via dielectric is formed that covers, and extends above, the line. A portion of the via dielectric layer above the composite protection/metal line is removed, exposing a portion of the protection surface of the composite protection/metal line. Finally, a portion of the protection surface from the composite protection/metal line is removed, leaving the metal portion of the line only.

Integrated circuits with borderless vias

A multilevel interconnect structure which has a first horizontal metallic conductor disposed on the top of a previously formed first contact/via dielectric where the contact/via dielectric contains a contact/via hole. A horizontal interconnect is deposited over the first contact/via dielectric and has a first surface defined by the thickness and linewidth of the horizontal interconnect. A vertical metallic conductor is deposited in the contact/via hole to form a contact/via plug which extends through the dielectric and contacts the first surface of the horizontal interconnect. The process may be used to form additional levels and to form a plurality of similar horizontal and vertical metallic interconnects.

Interconnect structures for integrated circuits

Surface-channel NMOS and PMOS transistors are formed in a CMOS compatible process by implanting the substrate to form source and drain regions at the same time that the gate is implanted to set the conductivity of the gate. Following this, a layer of dielectric is deposited and baked to densify and reflow the dielectric. The baked dielectric is then etched to expose the top surface of the gates. Next, a metallic layer is formed over the top surface of the gates. In accordance with the present invention, by forming the metallic layer after the dielectric layer has been baked, the degradation of the metallic layer that results from the baking is eliminated.

Method for forming a layer of metal silicide over the gates of a

A multilevel interconnect structure which has a first horizontal metallic conductor disposed on the top of a previously formed first contact/via dielectric where the contact/via dielectric contains a contact/via hole. A horizontal, interconnect is deposited over the first contact/via dielectric and has a first surface defined by the thickness and linewidth of the horizontal interconnect. A vertical metallic conductor is deposited in the contact/via hole to form a contact/via plug which extends through the dielectric and contacts the first surface of the horizontal interconnect. The process may be used to form additional levels and to form a plurality of similar horizontal and vertical metallic interconnects.

A method of forming interconnecting layers in a semiconductor device is such that, whereby even if a via is misaligned with a metal line, a portion of the via not enclosed by the metal is enclosed by an etch stop spacer. In addition, the via is always capped by the metal even if borders are not used in the design of the device. A metal layer is formed atop the foundation layer to cover the boundary layer, including completely filling the trench with metal. A protection layer is then formed on the surface of the metal layer. The protection layer and the metal layer are patterned to define a line of composite protection/metal on the surface of the foundation layer while leaving a remaining portion of the metal layer exclusive of the metal of the line. An etch stop layer is formed which substantially conforms to the shape of the line and to the remaining portion of the metal layer. Selected portions of the etch stop layer are removed to expose the protection surface of the line, and to leave etch stop spacers conforming to at least one sidewall portion of the line while exposing a sub-portion of the remaining portion of the metal layer. The exposed sub-portion of the metal layer is removed to expose a portion of the boundary layer, then the exposed portion of the boundary layer is removed. A layer of via dielectric is formed that covers and extends above the line. A portion of the via dielectric layer above the line is removed to expose a portion of the protection surface of the line. Finally, at least a portion of the protection surface is removed from the line, leaving the metal portion of the line only.

Fabrication of integrated circuits with borderless vias

A contact to a silicon semiconductor body is fabricated in a manner which merges the benefits of the low contact resistance provided by titanium silicide or cobalt silicide and the good step coverage provided by selective chemical vapor deposition (CVD) of tungsten or molybdenum from tungsten hexafluoride or molybdenum hexafluoride. An intermediate adhesion layer of molybdenum silicide or tungsten silicide is formed by physical vapor deposition, e.g., sputtering or vacuum evaporation, of molybdenum or titanium, followed by annealing. Such adhesion layer protects the underlying layer against damage by fluorine during CVD of the overlying layer of tungsten or molybdenum, as well as providing low resistance and good adhesion to both the underlying and overlying layers.

Method of forming conductive region on silicon semiconductor material,

A self-aligned thin-film ceramic oxide stacked capacitor on an underlying semiconductor substrate using a spin-on ceramic oxide fabricated by forming conductive pillars and the lower electrode, forming a temporary layer, building up the semiconductor substrate around the temporary layer, removing the temporary layer, and then spinning on the ceramic oxide. This results in a ceramic oxide stacked capacitor with the conformal thin-film ceramic oxide encapsulated by the top electrode.

Stacked capacitor with a thin film ceramic oxide layer

Electrical connections to specified semiconductor or electrically conductive portions (18, 26, and 30) of a structure created from a semiconductive body (10) are created by a process in which a titanium contact layer (34) is deposited on the structure over the specified portions. An electrically conductive barrier material layer (36) which consists principally of non-titanium refractory material is formed over the contact layer. The resulting structure is then annealed at a temperature above 550.degree. C. in order to lower the contact resistance. The anneal is preferably done at 600.degree. C. or more for 10-120 seconds in a gas whose principal constituent is nitrogen. An electrically conductive primary interconnect layer is formed over the barrier material layer after which all three layers are patterned to create a composite interconnect layer.

Growing community of inventors

Cupertino, CA, United States of America

Henry Wei-Ming Chung