E Ink Holdings Inc.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Entegris, Inc.

Prime View International Co. Ltd.

Henry Wang

Chia-Chun Yeh

Ted-Hong Shinn

Wei-Chou Lan

Xue-Hung Tsai

Yao-Chou Tsai

Fang-An Shu

Sung-Hui Huang

Wei-Tsung Chen

Po-Hsin Lin

Lee-Tyng Chen

Chih-Hsuan Wang

Wei-Cheng Wu

Kuo-Ching Huang

Harry-Hak-Lay Chuang

Hsiao-Wen Zan

Chuang-Chuang Tsai

Chien Hung Liu

Tsung-Hao Yeh

Hsin Fu Lin

Yi Wei Lu

Tung-Liang Lin

Bob Shie

Chi-Sheng Jiang

Dean Tsou

Fang An Shu

Hsien Jung Chen

A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Semiconductor-on-insulator (SOI) semiconductor structures including a high-k dielectric layer and methods of manufacturing the same

A method of making depth filtration media, such as for use in a depth filter, are described. The resulting depth filtration media includes a core tube having two or more different layers. The layers can be fibers, such as polymeric or inorganic fibers, wrapped layers of a filter material, or pleated and folded layers of a filter material.

Depth filtration media with multiple organic and/or inorganic materials

A pixel structure includes a substrate, a gate electrode disposed on the substrate, a capacitor electrode disposed on the substrate, a first insulation layer, an active layer disposed on the first insulation layer, a drain electrode, a source electrode and an extension electrode. The capacitor electrode is spaced apart from the gate electrode. The first insulation layer covers the gate electrode and the capacitor electrode. The first insulation layer has a recess vertically above the capacitor electrode. The drain and the source electrodes are disposed on the active layer and spaced apart from each other. The extension electrode extends from the drain electrode or the source electrode into the recess.

Pixel structure and display apparatus having the same

A display apparatus includes at least one pixel structure, which includes an active device, an electric insulation layer and a pixel electrode. The electric insulation layer is disposed on the active device. The electric insulation layer has a trench and a via. The via is located on a bottom surface of the trench. A portion of the electric insulation layer surrounding the trench is monolithically connected to another portion of the electric insulation layer surrounding the via. A pixel electrode has a first electrode portion and a second electrode portion connected to each other. The first electrode portion is located in the trench. A thickness of the first electrode portion is less than a depth of the trench. The second electrode portion is located in the via and is electrically connected to the active device through the via.

Display apparatus and pixel structure thereof

A display device includes a substrate and a peripheral circuit structure on the substrate. The peripheral circuit includes a common electrode layer between the ESD protection diode and a pixel unit of the substrate, an ESD protection diode, an isolation layer covering the common electrode layer, a first conductive line on the isolation layer and over the common electrode layer, and a second conductive line on the isolation layer and over the common electrode layer. Two ends of the first conductive line are respectively electrically connected to the ESD protection diode and the pixel unit. Two ends of the second conductive line are electrically connected to the first conductive line on positions that are between the ESD protection diode and the common electrode layer and between the pixel unit and the common electrode layer to respectively form a first junction and a second junction.

Display device and peripheral circuit structure thereof

A metal oxide thin film transistor (TFT) includes a gate electrode, a gate insulating layer, a metal oxide active layer, a source electrode, and a drain electrode. The gate electrode is formed on a substrate. The gate insulating layer is formed on the substrate and covers the gate electrode. The metal oxide active layer is formed on the gate insulating layer. The drain electrode and the source electrode are formed on two opposite ends of the metal oxide active layer in a spaced-apart manner, in which at least one of the orthographic projection of the source electrode and the orthographic projection of the drain electrode on the substrate does not overlap the gate electrode.

Metal oxide thin film transistor

Disclosed herein is a method for manufacturing an array substrate. The method includes forming a source electrode and a drain electrode on a substrate. A semiconductor layer, an organic insulating layer, and a gate electrode layer are sequentially formed to cover the substrate, the source electrode, and the drain electrode. A patterned photoresist layer is formed on the gate electrode layer. The exposed portion of the gate electrode layer, and a portion of the organic insulative layer and a portion of the semiconductor layer thereunder are removed to form a gate electrode. An organic passivation layer is formed on the gate electrode, the source electrode, and the drain electrode. The organic passivation layer has a contact window to expose a portion of the drain electrode. A pixel electrode is formed on the organic passivation layer and the exposed portion of the drain electrode.

Array substrate and method for manufacturing the same

A thin film transistor (TFT) including a gate, a dielectric layer, a metal-oxide semiconductor channel, a source, and a drain is provided. The gate and the metal-oxide semiconductor channel are overlapped. The gate, the source, and the drain are separated by the dielectric layer. Besides, the source and the drain are respectively located on two opposite sides of the metal-oxide semiconductor channel. The metal-oxide semiconductor channel includes a metal-oxide semiconductor layer and a plurality of nano micro structures disposed in the metal-oxide semiconductor layer and separated from one another. In another aspect, a display panel including the TFT and a method of fabricating the TFT are also provided.

Display panel, thin film transistor and method of fabricating the same

Disclosed herein is a thin film transistor. The thin film transistor is characterized in having a source interconnect layer and a drain interconnect layer. The source electrode and the drain electrode are respectively disposed above and in contact with the source interconnect layer and the drain interconnect layer. The semiconductor layer is in contact with both the source interconnect layer and the drain interconnect layer, but is not in contact with the source electrode and the drain electrode.

Thin-film transistor and method for manufacturing the same

An exemplary driving substrate includes a substrate, a plurality of first and second signal transmission lines, a first insulation layer and a plurality of switch devices. The first signal transmission lines are disposed on the substrate, and each includes a first line segment(s) and a first connecting segment(s). The first insulation layer is disposed between each first line segment and each first connecting segment, and each first connecting segment is electrically connected to the adjacent first line segment(s) through an opening(s) of the first insulation layer. The second signal transmission lines are disposed on the substrate and electrically insulated and intersected with the first signal transmission lines thereby defining a plurality of pixel regions on the substrate. The switch devices are respectively disposed in the pixel regions, and each is electrically connected to corresponding first and second signal transmission lines. The driving substrate has better reliability.

Driving substrate and display apparatus using the same

A thin film transistor suitable for being disposed on a substrate is provided. The thin film transistor includes a gate electrode, an organic gate dielectric layer, a metal oxide semiconductor layer, a source electrode and a drain electrode. The gate electrode is disposed on the substrate. The organic gate dielectric layer is disposed on the substrate to cover the gate electrode. The source electrode, the drain electrode and the metal oxide semiconductor layer are disposed above the organic gate dielectric layer, and the metal oxide semiconductor layer contacts with the source electrode and the drain electrode. Because the channel layer of the thin film transistor is a layer of metal oxide semiconductor formed at a lower temperature, thus the thin film transistor can be widely applied into various display applications such as flexible display devices.

Thin film transistor

A semiconductor device including a substrate, a metal layer, an insulating layer, a semiconductor layer, a drain and a source is provided. The substrate has a surface and a first cavity. The metal layer is disposed on the substrate and covers the surface and inner-wall of the first cavity to define a second cavity corresponding to the first cavity. The insulating layer covers the metal layer and inner-wall of the second cavity to define a third cavity corresponding to the second cavity. The semiconductor layer exposes a portion of the insulating layer and covers the inner-wall of the third cavity to define a fourth cavity corresponding to the third cavity. The drain and source are disposed on the semiconductor layer and covers a portion of the semiconductor layer and a portion of the insulating layer, in which the drain and source expose the fourth cavity.

Growing community of inventors

Hsinchu, Taiwan

Henry Wang